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PDF CY7C264 Data sheet ( Hoja de datos )
| Número de pieza | CY7C264 | |
| Descripción | 8K x 8 Power-Switched and Reprogrammable PROM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY7C264 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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CY7C261
CY7C263/CY7C264
8K x 8 Power-Switched and Reprogrammable PROM
Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
— 20 ns (Commercial)
— 25 ns (Military)
• Low power
— 660 mW (Commercial)
— 770 mW (Military)
• Super low standby power (7C261)
— Less than 220 mW when deselected
— Fast access: 20 ns
• EPROM technology 100% programmable
• Slim 300-mil or standard 600-mil packaging available
• 5V ± 10% VCC, commercial and military
• Capable of withstanding greater than 2001V static
discharge
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
Functional Description
The CY7C261, CY7C263, and CY7C264 are high-perfor-
mance 8192-word by 8-bit CMOS PROMs. When deselected,
the CY7C261 automatically powers down into a low-power
standby mode. It is packaged in a 300-mil-wide package. The
CY7C263 and CY7C264 are packaged in 300-mil-wide and
600-mil-wide packages respectively, and do not power down
when deselected. The reprogrammable packages are
equipped with an erasure window; when exposed to UV light,
these PROMs are erased and can then be reprogrammed.
The memory cells utilize proven EPROM floating-gate
technology and byte-wide intelligent programming algorithms.
The CY7C261, CY7C263, and CY7C264 are plug-in replace-
ments for bipolar devices and offer the advantages of lower
power, superior performance and programming yield. The
EPROM cell requires only 12.5V for the supervoltage and low
current requirements allow for gang programming. The
EPROM cells allow for each memory location to be tested
100%, as each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer
programming the product will meet DC and AC specification
limits.
Read is accomplished by placing an active LOW signal on CS.
The contents of the memory location addressed by the
address line (A0−A12) will become available on the output lines
(O0−O7).
Logic Block Diagram
A0
A1
A2
A3
ROW
ADDRESS
A4
A5
A6
A7
ADDRESS
DECODER
A8
A9
A10 COLUMN
A11 ADDRESS
A12
CS
PROGRAM-
MABLE
ARRAY
COLUMN
MULTI-
PLEXER
POWER DOWN
(7C261)
Pin Configurations
O7
DIP/Flatpack
O6
Top View
A7 1
24 VCC
LCC/PLCC (OpaqueOnly)
Top View
A6 2
23 A8
O5
O4
A5 3
A4 4
A3 5
A2 6
A1 7
22 A9
21 A10
20 CS
19 A11
18 A12
4 3 2 1 28 27 26
A4 5
25 A10
A3 6
A2 7
A1 8
7C261
7C263
24 CS
23 A11
22 A12
O3
A0
O0
8 7C261 17
9
7C263
7C264 16
O7
O6
O1 10
15 O5
A0 9
21 NC
NC 10
20 O7
O0 11
19 O6
12 1314151617 18
O2
O2 11
14 O4
GND 12
13 O3
O1
O0
For an 8K x 8 Registered PROM, see theCY7C265.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-04010 Rev. *B
Revised December 28, 2002
1 page  
Switching Waveforms[4]
VCC
SUPPLY
CURRENT
A0 - A12
ADDRESS
CS
O0 - O7
tAA
tPD
50%
tHZCS
CY7C261
CY7C263/CY7C264
tPU
50%
tACS
Erasure Characteristics
Wavelengths of light less than 4000 angstroms begin to erase
the devices in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM
is exposed to sunlight or fluorescent lighting for extended
periods of time.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 angstroms for a minimum dose (UV
intensity multiplied by exposure time) of 25 Wsec/cm2. For an
ultraviolet lamp with a 12 mW/cm2 power rating, the exposure time
would be approximately 35 minutes. The 7C261 or 7C263
needs to be within 1 inch of the lamp during erasure.
Permanent damage may result if the PROM is exposed to
high-intensity UV light for an extended period of time. 7258
Wsec/cm2 is the recommended maximum dosage.
Operating Modes
Read
Read is the normal operating mode for programmed device. In
this mode, all signals are normal TTL levels. The PROM is
addressed with a 13-bit field, a chip select, (active LOW), is
applied to the CS pin, and the contents of the addressed location
appear on the data out pins.
Program, Program Inhibit, Program Verify
These modes are entered by placing a high voltage VPP on pin
19, with pins 18 and 20 set to VILP. In this state, pin 21 becomes a
latch signal, allowing the upper 5 address bits to be latched into an
onboard register, pin 22 becomes an active LOW program (PGM)
signal and pin 23 becomes an active LOW verify (VFY) signal. Pins
22 and 23 should never be active LOW at the same time. The
PROGRAM mode exists when PGM is LOW, and VFY is HIGH. The
verify mode exists when the reverse is true, PGM HIGH and VFY
LOW and the program inhibit mode is entered with both PGM and
VFY HIGH. Program inhibit is specifically provided to allow data to be
placed on and removed from the data pins without conflict
Table 1. Mode Selection
Read or Output Disable A12
A11
A10
Mode
Program
NA VPP
LATCH
Read
A12 A11
A10
Output Disable
A12 A11
A10
Program
VILP
VPP
VILP
Program Inhibit
VILP
VPP
VILP
Program Verify
VILP
VPP
VILP
Blank Check
VILP
VPP
VILP
Notes:
6. X = “don’t care” but not to exceed VCC ±5%.
7. Addresses A8-A12 must be latched through lines A0-A4 in programming modes.
Pin Function[6, 7]
A9
PGM
A8
VFY
A9
A9
VILP
VIHP
VIHP
VIHP
A8
A8
VIHP
VIHP
VILP
VILP
CS
CS
VIL
VIH
VILP
VILP
VILP
VILP
O7–O0
D7–D0
O7–O0
High Z
D7–D0
High Z
O7–O0
O7–O0
Document #: 38-04010 Rev. *B
Page 5 of 14
5 Page 
Package Diagrams (continued)
24-Lead (600-Mil) Molded DIP P11
CY7C261
CY7C263/CY7C264
24-Lead (300-Mil) Molded DIP P13/P13A
51-85016-A
51-85013-A
Document #: 38-04010 Rev. *B
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY7C264.PDF ] | |
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