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GLT5160L16-10FJ Schematic ( PDF Datasheet ) - ETC

Teilenummer GLT5160L16-10FJ
Beschreibung 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
Hersteller ETC
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Gesamt 30 Seiten
GLT5160L16-10FJ Datasheet, Funktion
GLT5160L16
16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
ADVANCED
FEATURES
u Single 3.3 V ±0.3 V power supply
u Clock frequency 100 MHz / 125 MHz / 143 MHz/
166 MHz
u Fully synchronous operation referenced to clock rising edge
u Dual bank operation controlled by BA (Bank Address)
u CAS latency- 2 / 3 (programmable)
u Burst length- 1 / 2 / 4 / 8 & Full Page (programmable)
u Burst type- sequential / interleave (programmable)
u Industrial grade available
GENERAL DESCRIPTION
The GLT5160L16 is a 2-bank x 524288-word x 16-bit Synchro-
nous DRAM, with LVTTL interface. All inputs and outputs are
referenced to the rising edge of CLK. The GLT5160L16 achieves
u Byte control by DQMU and DQML
u Column access - random
u Auto precharge / All bank precharge controlled by A[10]
u Auto refresh and Self refresh
u 4096 refresh cycles / 64 ms
u LVTTL Interface
u 400-mil, 50-Pin Thin Small Outline Package (TSOP II) with
0.8 mm lead pitch
u 60-Ball, 6.4mmx10.1mm VFBGA package with 0.65mm Ball
pitch & 0.35mm Ball diameter.
very high speed data rate up to 166 MHz, and is suitable for main
memory or graphic memory in computer systems.
DEC. 2003 (Rev.2.4) 1






GLT5160L16-10FJ Datasheet, Funktion
Function Truth Table [1] [2] (Continued)
Current State
REFRESHING
MODE REGISTER
SETTING
CS RAS CAS WE
Address [3]
Command
H X X XX
DESEL
L H H HX
NOP
L H H LX
TBST
L H L X BA, CA, A[10]
READ / WRITE
L L H H BA, RA
ACT
L L H L BA, A[10]
PRE / PREA
L L L HX
REFA
L L L L Op-Code, Mode-Add MRS
H X X XX
DESEL
L H H HX
NOP
L H H LX
TBST
L H L X BA, CA, A[10]
READ / WRITE
L L H H BA, RA
ACT
L L H L BA, A[10]
PRE / PREA
L L L HX
REFA
L L L L Op-Code, Mode-Add MRS
Action [4]
NOP (Idle after tRC)
NOP (Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Idle after tRSC)
NOP (Idle after tRSC)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
1. H = High Level, L= Low Level, X = Don't Care.
2. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
3. BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No OPeration.
4. ILLEGAL = Device operation and/or data-integrity are not guaranteed.
5. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.
6. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
7. ILLEGAL if any bank is not idle.
8. Must satisfy bus contention, bus turn around, write recovery requirements.
6 G-LINK Technology
DEC. 2003 (Rev. 2.4)

6 Page









GLT5160L16-10FJ pdf, datenblatt
Write
After tRCD from the bank activation, a WRITE command can be
issued. 1st input data is set at the same cycle as the WRITE. Follow-
ing (BL-1) data are written into the RAM, when the Burst Length is
BL. The start address is specified by A[7:0], and the address
sequence of burst data is defined by the Burst Type. A WRITE com-
mand may be applied to any active bank, so the row precharge time
(tRP) can be hidden behind continuous input data (in case of BL = 4)
by interleaving the dual banks. From the last input data to the PRE
command, the write recovery time (tRDL) is required. When A[10]
is high at a WRITE command, the auto-precharge (WRITEA) is
performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited till the internal precharge is complete. The
internal precharge begins at tWR after the last input data cycle. The
next ACT command can be issued after tRP from the internal pre-
charge timing.
CLK
Command
A[9:0]
A[10]
BA
DQ
ACT
Xa
Xa
0
tRCD
WRITE ACT
Y Xb
0 Xb
tRCD
WRITE PRE
Y
tRDL (1
0
0
01
10
Burst Length
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
Figure 7. Dual Bank Interleaving WRITE (BL=4)
CLK
Command
A[9:0]
A[10]
BA
DQ
ACT
Xa
Xa
0
tRCD
WRITE
Y
1
0
Da0 Da1
tRDL
Da2 Da3
ACT
tRP
Xa
Xa
0
Internal Precharge Begins
Figure 8. WRITE with Auto-Precharge (BL=4)
12 G-LINK Technology
DEC. 2003 (Rev. 2.4)

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