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R5F571MJDDBG Schematic ( PDF Datasheet ) - Renesas

Teilenummer R5F571MJDDBG
Beschreibung 240-MHz 32-bit RX MCU
Hersteller Renesas
Logo Renesas Logo 




Gesamt 30 Seiten
R5F571MJDDBG Datasheet, Funktion
Features
Datasheet
RX71M Group
Renesas MCUs
R01DS0249EJ0100
Rev.1.00
240-MHz 32-bit RX MCU, on-chip FPU, 480 DMIPS, up to 4-MB flash memory,
Jan 15, 2015
512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC,
high-speed USB 2.0 with battery charging, SD host interface (optional), quad SPI, and CAN, 12-bit A/D
converter, RTC, encryption (optional), serial interface for audio, CMOS camera interface
Features
32-bit RXv2 CPU core
Max. operating frequency: 240 MHz
Capable of 480 DMIPS in operation at 240 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU clock
cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
JTAG and FINE (one-line) debugging interfaces
Low-power design and architecture
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral
functions draws only 0.2mA/MHz (Typ.).
RTC is capable of operation from a dedicated power supply.
Four low-power modes
On-chip code flash memory
Supports versions with up to 4 Mbytes of ROM
No wait states at up to 120 MHz or when the AFU is hit, one wait
state at above 120 MHz and when the AFU is missed
User code is programmable by on-board or off-board programming.
Programming/erasing as background operations (BGOs)
On-chip data flash memory
64 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
On-chip SRAM
512 Kbytes of SRAM (no wait states except in the 256 Kbytes from
0004 0000h to 0007 FFFFh when ICLK is set to 120 MHz or faster)
32 Kbytes of RAM with ECC (single-error correction and double
error detection)
8 Kbytes of standby RAM (backup on deep software standby)
Data transfer
DMAC: 8 channels
DTC
EXDMAC: 2 channels
DMAC for the Ethernet controller: 3 channels for 176- and 177-pin
products; 2 channels for 100-, 144-, and 145-pin products
Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External crystal oscillator or internal PLL for operation at 8 to 24
MHz
Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20
MHz
120-kHz clock for the IWDTa
Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Real-time clock counting and binary counting modes are selectable
Time capture function
(for capturing times in response to event-signal input)
Independent watchdog timer
120-kHz (1/2 LOCO frequency) clock operation
Useful functions for IEC60730 compliance
Oscillation-stoppage detection, frequency measurement, CRC,
IWDTa, self-diagnostic function for the A/D converter, etc.
Register write protection function can protect values in important
registers against overwriting.
PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch
PLQP0144KA-A 20 × 20 mm, 0.5-mm pitch
PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch
PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch
PLBG0176GA-A 13 × 13mm, 0.8-mm pitch
Various communications interfaces
IEEE 1588-compliant Ethernet MAC
(for 176- and 177-pin products: 2 modules)
PHY layer for host/function or OTG controller (1) with high-speed
USB 2.0 with battery charging transfer (only for 176- and 177-pin
products)
PHY layer (1) for host/function or OTG controller (1) with full-
speed USB 2.0 transfer
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up
to 3 modules)
SCIg and SCIh with multiple functionalities (up to 9)
Choose from among asynchronous mode, clock-synchronous mode,
smart-card interface mode, simplified SPI, simplified I2C, and
extended serial mode.
SCIFA with 16-byte transmission and reception FIFOs (up to 4
interfaces)
I2C bus interface for transfer at up to 1 Mbps (up to 2 interfaces)
Four-wire QSPI (1 interface) in addition to RSPIa (2 interfaces)
Parallel data capture unit (PDC) for the CMOS camera interface (not
in 100-pin products)
SD host interface (optional: 1 interface) with a 1- or 4-bit SD bus for
use with SD memory or SDIO
MMCIF with 1-, 4-, or 8-bit transfer bus width
External address space
Buses for full-speed data transfer (max. operating frequency of 60
MHz)
8 CS areas
8-, 16-, or 32-bit bus space is selectable per area
Independent SDRAM area (128 Mbytes)
Up to 29 extended-function timers
16-bit TPUa, MTU3a, and GPTa: input capture, output compare,
PWM waveform output
8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2
channels)
12-bit A/D converter
Two 12-bit units (8 channels for unit 0; 21 channels for unit 1)
Self diagnosis
Detection of analog input disconnection
12-bit D/A converter: 2 channels
On-chip operational amplifier output or direct input selectable
Temperature sensor for measuring temperature
within the chip
Encryption (optional)
AES (key lengths: 128, 196, and 256 bits)
DES (key lengths: 56 bits (DES); 3 × 56 bits (T-DES))
SHA (SHA-1 (128), SHA-2 (224 or 256), HMAC (160, 224, or 256))
Up to 127 pins for general I/O ports
5-V tolerance, open drain, input pull-up, switchable driving ability
Operating temp. range
–40C to +85C
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 1 of 228






R5F571MJDDBG Datasheet, Funktion
RX71M Group
1. Overview
Table 1.1
Outline of Specifications (5/10)
Classification
Timers
Module/Function
General PWM timer
(GPTa)
Programmable pulse
generator (PPG)
8-bit timers (TMRb)
Compare match timer
(CMT)
Compare match timer
W (CMTW)
Realtime clock (RTCd)
Watchdog timer
(WDTA)
Independent watchdog
timer (IWDTa)
Description
16 bits × 4 channels
Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for
all channels
Four clock sources independently selectable for all channels (PCLKA/1, PCLKA/4,
PCLKA/8, PCLKA/16)
2 input/output pins per channel
2 output compare/input capture registers per channel
For the 2 output compare/input capture registers of each channel, 4 registers are
provided as buffer registers and are capable of operating as comparison registers when
buffering is not in use.
In output compare operation, buffer switching can be at peaks or troughs, enabling the
generation of laterally asymmetrically PWM waveforms.
Registers for setting up frame intervals on each channel (with capability for generating
interrupts on overflow or underflow)
Synchronizable operation of the several counters
Modes of synchronized operation (synchronized, or displaced by desired times for
phase shifting)
Generation of dead times in PWM operation
Through combination of three counters, generation of automatic three-phase PWM
waveforms incorporating dead times
Starting, clearing, and stopping counters in response to external or internal triggers
Internal trigger sources: output of the internal comparator detection, software, and
compare-match
Digital filter function for signals on the input capture and external trigger pins
Event linking by the ELC
(4 bits × 4 groups) × 2 units
Pulse output with the MTU or TPU output as a trigger
Maximum of 32 pulse-output possible
(8 bits × 2 channels) × 2 units
Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8,
PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
Event linking by the ELC
(16 bits × 2 channels) × 2 units
Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,
PCLKB/512)
Event linking by the ELC
(32 bits × 1 channel) × 2 units
Compare-match, input-capture input, and output-comparison output are available.
Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,
PCLKB/512)
Interrupt requests can be output in response to compare-match, input-capture, and
output-comparison events.
Event linking by the ELC
Clock sources: Main clock, sub clock
Selection of the 32-bit binary count in time count/second unit possible
Clock and calendar functions
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Battery backup operation
Time-capture facility for three values
Event linking by the ELC
14 bits × 1 channel
Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128,
PCLKB/512, PCLKB/2048, PCLKB/8192)
14 bits × 1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
Window function: The positions where the window starts and ends are specifiable (the
window defines the timing with which refreshing is enabled and disabled).
Event linking by the ELC
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 6 of 228

6 Page









R5F571MJDDBG pdf, datenblatt
RX71M Group
1. Overview
Table 1.2
Comparison of Functions for Different Packages (1/2)
Functions
RX71M Group
Package
177 Pins, 176 Pins 145 Pins, 144 Pins 100 Pins
External bus
External bus width
32 bits
16 bits
SDRAM area controller
Available
Not supported
DMA
DMA controller
Ch. 0 to 7
Data transfer controller
Available
EXDMA controller
Ch. 0 and 1
Timers
16-bit timer pulse unit
Ch. 0 to 5
Multi-function timer pulse unit 3
General-purpose PWM timer
Port output enable 3
Programmable pulse generator
Ch. 0 to 8
Ch. 0 to 3
Available
Ch. 0 and 1
8-bit timers
Ch. 0 to 3
Compare match timer
Ch. 0 to 3
Compare match timer W
Ch. 0 and 1
Realtime clock
Available
Watchdog timer
Available
Independent watchdog timer
Available
Communication Ethernet controller
function
PTP controller for ethernet controller
Ch. 0 and 1
Available
Ch. 0
DMAC controller for ethernet
Ch. 0 and 1 (ETHERC)
Ch. 2 (EPTPC)
Ch. 0 (ETHERC) and 2 (EPTPC)
USB 2.0 FS host/function module
Ch. 0
USB 2.0 HS host/function module with battery
charging
Available
Not supported
Serial communications interfaces (SCIg)
Ch. 0 to 7
Ch. 0 to 3, 5 and 6
Serial communications interfaces (SCIh)
Ch. 12
Serial communications interfaces with FIFO
I2C bus interfaces
Ch. 8 to 11
Ch. 0 and 2
Ch. 8 and 9
Serial peripheral interface
Ch. 0 and 1
CAN module
Ch. 0 to 2
Ch. 0 and 1
Quad serial peripheral interface
Ch. 0
Serial sound interfaces
Sampling rate converter
SD host interface
Ch. 0 and 1
Available
Ch. 0
MMC host interface
Ch. 0
Parallel data capture unit
Available
Not supported
12-bit A/D converter
AN000 to 007 (unit 0: 8 channels)
AN100 to 120 (unit 1: 21 channels)
AN000 to 007
(unit 0: 8 channels)
AN100 to 113
(unit 1: 14
channels)
12-bit D/A converter
Ch. 0 and 1
Ch. 1
Temperature sensor
Available
CRC calculator
Available
Data operation circuit
Available
Clock frequency accuracy measurement circuit
AES
Available
Available
R01DS0249EJ0100 Rev.1.00
Jan 15, 2015
Page 12 of 228

12 Page





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