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ADAR7251 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADAR7251
Beschreibung 4-Channel / 16-Bit / Continuous Time Data Acquisition ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADAR7251 Datasheet, Funktion
Data Sheet
4-Channel, 16-Bit, Continuous Time
Data Acquisition ADC
ADAR7251
FEATURES
Low noise: 2.4 nV/√Hz input referred voltage noise at
maximum gain setting
Wide input signal bandwidth: 500 kHz at 1.2 MSPS sample
rate, 16-bit resolution
Additional sample rates supported: 300 kSPS, 450 kSPS,
600 kSPS, 900 kSPS, and 1.8 MSPS
4 differential simultaneous sampling channels
No active antialiasing filter required
LNA and PGA with 45 dB gain range in 6 dB steps
Selectable equalizer
Flexible data port supports serial or parallel mode
Supports FSK mode for FMCW radar systems
On-chip 1.5 V reference
Internal oscillator/PLL input: 16 MHz to 54 MHz
High speed serial data interface
SPI control
2 general-purpose inputs/outputs
48-lead LFCSP_SS package
Temperature range: −40°C to +125°C
Single supply operation of 3.3 V
Qualified for automotive applications
APPLICATIONS
Automotive LSR systems
Data acquisition systems
GENERAL DESCRIPTION
The ADAR7251 is a 16-bit, 4-channel, simultaneous sampling
analog-to-digital converter (ADC) designed especially for
applications such as automotive LSR-FMCW or FSK-FMCW
radar systems. Each of the four channels contains a low noise
amplifier (LNA), a programmable gain amplifier (PGA), an
equalizer, a multibit Σ-Δ ADC, and a decimation filter.
The front-end circuitry is designed to allow direct connection
to an MMIC output with few external passive components. The
ADAR7251 eliminates the need for a high order antialiasing
filter, driver op amps, and external bipolar supplies. The
ADAR7251 also offers precise channel-to-channel drift
matching.
The ADAR7251 features an on-chip phase-locked loop (PLL)
that allows a range of clock frequencies for flexibility in the system.
The CONV_START input and DATA_READY output signals
synchronize the ADC with an external ramp for applications such
as FSK-FMCW radar.
The ADAR7251 supports serial and parallel interfaces at
programmable sample rates from 300 kSPS to 1.8 MSPS, as well
as easy connections to digital signal processors (DSPs) and
microcontroller units (MCUs) in the system.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
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ADAR7251 Datasheet, Funktion
ADAR7251
Data Sheet
Parameter
ANALOG INPUT
Full-Scale Differential Voltage
Common-Mode Rejection Ratio (CMRR)
Gain Error
Input Resistance
VOLTAGE REFERENCE IN/OUT (VREF)
CONVERSION SAMPLE RATE
Sample Rate
Input Signal Bandwidth
PLL
Input Frequency
Output Frequency (Internal)
Lock Time
LDO
REGOUT_DIGITAL Output Voltage
Line Regulation
Load Regulation
AUXILIARY ADC
Full-Scale Input
Sample Rate
Resolution
INL
DNL
Input Resistance1
Test Conditions/Comments
Gain = 0 dB (LNA and PGA bypass)
Gain = 9 dB
Gain = 15 dB
Gain = 21 dB
Gain = 27 dB
Gain = 33 dB
Gain = 39 dB
Gain = 45 dB
At 1 kHz
Single-ended
Differential
At the CM pin
Min
−0.8
0.3
150
16
Used for internal digital core only
AVDDx as an input
Used for internal digital core only
2.97
112.5
Switched capacitor input at a switching
frequency of 112.5 kHz
Typ
5.6
1.987
0.995
0.498
249
124
62
31
68
2860
5720
1.5
1.2
600
115.2
1
1.8
3.3
1
3.3
8
0.5
1
1.2
1 From simulation.
DIGITAL INPUT/OUTPUT
DVDDx = 1.8 V, IOVDDx = 3.3 V, CLOAD = 22 pF.
Table 2.
Parameter
INPUT VOLTAGE
High Level
Low Level
OUTPUT VOLTAGE
High Level
Low Level
INPUT CAPACITANCE
INPUT LEAKAGE CURRENT
Symbol
VIH
VIL
VOH
VOL
Test Conditions/Comments
IOH = 1 mA
IOL = 1 mA
Min
0.7 × IOVDDx
Typ
IOVDDx − 0.60
Max Unit
V p-p
V p-p
V p-p
V p-p
mV p-p
mV p-p
mV p-p
mV p-p
dB
+0.8 dB
Ω
Ω
V
1.8 MSPS
900 kHz
54 MHz
MHz
ms
V
3.63 V
%
V p-p
450 kHz
bits
LSB
LSB
Max Unit
0.3 × IOVDDx
V
V
V
0.4 V
5 pF
±10 μA
Rev. 0 | Page 6 of 72

6 Page









ADAR7251 pdf, datenblatt
ADAR7251
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND1 1
AIN3P 2
AIN3N 3
AIN4P 4
AIN4N 5
AUXIN1 6
AUXIN2 7
CM 8
AGND2 9
BIASN 10
BIASP 11
AVDD1 12
ADAR7251
TOP VIEW
(Not to Scale)
36 DGND3
35 CONV_START
34 SCLK_ADC
33 FS_ADC/ADC_DOUT7
32 ADDR15/ADC_DOUT6
31 ADC_DOUT5
30 ADC_DOUT4
29 ADC_DOUT3/GPIO2
28 ADC_DOUT2/GPIO1
27 ADC_DOUT1
26 ADC_DOUT0
25 IOVDD1
Data Sheet
NOTES
1. THE EXPOSED PAD ON THE BOTTOM OF THE PACKAGE MUST BE
SOLDERED TO THE GROUND PLANE ON THE BOARD FOR POWER DISSIPATION.
Figure 7. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic
Type1
EPAD
1 AGND12
2 AIN3P
3 AIN3N
4 AIN4P
5 AIN4N
6 AUXIN1
7 AUXIN2
8 CM
PWR
AIN
AIN
AIN
AIN
AIN
AIN
AIO
9 AGND22
10 BIASN
11 BIASP
12 AVDD1
13 PLLGND
14 PLLFILT
15 PLLVDD
PWR
AOUT
AOUT
PWR
PWR
AIN
PWR
16 XIN/MCLKIN
AIN
17 XOUT
AOUT
18 AVDD2
PWR
19
REGOUT_DIGITAL
PWR
20 DGND13
PWR
Description
Exposed Pad. The exposed pad on the bottom of the package must be soldered to the ground plane
on the board for power dissipation.
Analog Ground. This pin is the ground reference point for all analog blocks in the ADAR7251.
Noninverting Input to Differential Analog Channel 3.
Inverting Input to Differential Analog Channel 3.
Noninverting Input to Differential Analog Channel 4.
Inverting Input to Differential Analog Channel 4.
Auxiliary ADC Analog Input 1. Single-ended analog input channel.
Auxiliary ADC Analog Input 2. Single-ended analog input channel.
ADC Reference Output. Connect a 10 μF capacitor in parallel with a 100 nF capacitor from this pin to
AGNDx.
Analog Ground. This pin is the ground reference point for all analog blocks in the ADAR7251.
Internal Bias Generator. Decouple to AGNDx using a 0.47 μF capacitor.
Internal Bias Generator. Decouple to AVDDx using a 0.47 μF capacitor.
Analog Supply Voltage, 3.3 V. Decouple this supply pin to AGNDx. See Figure 60.
Analog Ground for PLL. Connect to a ground plane directly on the board.
Filter Components Connection for PLL. See Figure 60.
Analog Supply for Analog PLL, 3.3 V. Decouple to the PLLGND pin (Pin13) using a 0.1 μF multilayer
ceramic capacitor (MLCC). Connect to AVDDx or an external 3.3 V source. It is recommended to add
the filter for a clean 3.3 V source and for good PLL performance.
Internal Oscillator Input/Clock Input. If using an external crystal, connect it between the XIN and
XOUT pins. If not using a crystal, a single-ended clock must be provided at the MCLKIN pin. The
ADAR7251 accepts a clock frequency range of 16 MHz to 54 MHz.
Internal Oscillator Output Connection for External Crystal.
Analog Supply Voltage, 3.3 V. Decouple this supply pin to AGNDx. See Figure 60.
LDO Regulator Output for Internal Digital Core (1.8 V, Typical). Decouple to DGNDx. See Figure 60. Connect
REGOUT_DIGITAL to the DVDDx pins if using the internal regulator to supplythe 1.8 V to the digital core.
Digital Ground. This pin is the ground reference point for the digital circuitry on the ADAR7251.
Rev. 0 | Page 12 of 72

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