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GS72108J-15 Schematic ( PDF Datasheet ) - ETC

Teilenummer GS72108J-15
Beschreibung 256K x 8 2Mb Asynchronous SRAM
Hersteller ETC
Logo ETC Logo 




Gesamt 12 Seiten
GS72108J-15 Datasheet, Funktion
GS72108TP/J
SOJ, TSOP
Commercial Temp
Industrial Temp
Features
256K x 8
2Mb Asynchronous SRAM
8, 10, 12, 15 ns
3.3 V VDD
Center VDD and VSS
SOJ 256K x 8-Pin Configuration
• Fast access time: 8, 10, 12, 15 ns
• CMOS low power operation: 150/125/110/90 mA at
minimum cycle time.
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 36-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
Description
The GS72108 is a high speed CMOS Static RAM organized as
262,144 words by 8 bits. Static design eliminates the need for
external clocks or timing strobes. The GS operates on a single
3.3 V power supply and all inputs and outputs are TTL-com-
patible. The GS72108 is available in 400 mil SOJ and 400 mil
TSOP Type-II packages.
Pin Descriptions
Symbol
A0A17
DQ1DQ8
CE
WE
OE
VDD
VSS
NC
Description
Address input
Data input/output
Chip enable input
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
A4 1
A3 2
A2 3
A1 4
A0 5
CE 6
DQ1 7
DQ2 8
VDD 9
VSS 10
DQ3 11
DQ4 12
WE 13
A17 14
A16 15
A15 16
A14 17
A13 18
36-pin
400 mil SOJ
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A5
A6
A7
A8
OE
DQ8
DQ7
VSS
VDD
DQ6
DQ5
A9
A10
A11
A12
NC
NC
Rev: 1.08 7/2002
1/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.






GS72108J-15 Datasheet, Funktion
AC Characteristics
GS72108TP/J
Read Cycle
Parameter
-8 -10 -12 -15
Symbol
Unit
Min Max Min Max Min Max Min Max
Read cycle time
Address access time
Chip enable access time (CE)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
tRC 8 10 12 15 ns
tAA 8 10 12 15 ns
tAC 8 10 12 15 ns
tOE 3.5 4 5 6 ns
tOH 3 3 3 3 ns
tLZ* 3 3 3 3 ns
tOLZ* 0 0 0 0 ns
tHZ* 4 5 6 7 ns
tOHZ* 3.5 4 5 6 ns
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = VIL, WE = VIH
Address
Data Out
tOH
Previous Data
tRC
tAA
Data valid
Rev: 1.08 7/2002
6/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.

6 Page









GS72108J-15 pdf, datenblatt
Revision History
Rev. Code: Old;
New
72108 1.04d 5/1999/721081.05 1/
2000
GS72108TP/J
Types of Changes
Format or Content
Page #/Revisions/Reason
Content
• Page 2/Pins 16–20 and 26–30 on 44-pin TSOP II Pin Configuration/
Correction
GS72108Rev1.05 10/19991/
2000K;Rev 5 2/2000L
721081.05 1/2000
72108_r1_07; 72108_r1_08
Format/Content
Content
Format
Content
• GSI Logo
• Corrected TSOP-II pin configuration diagram (A17–A13 in lower left
quadrant; A9–A12, A18 in lower right quadrant)
• Updated format to comply with Technical Publications standard
• Specifically noted that numbers in Power Supply Currents table are worst
case scenario
• Removed all references to “U” package
Rev: 1.08 7/2002
12/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.

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