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GS70328SJ-8I Schematic ( PDF Datasheet ) - ETC

Teilenummer GS70328SJ-8I
Beschreibung 32K x 8 256Kb Asynchronous SRAM
Hersteller ETC
Logo ETC Logo 




Gesamt 12 Seiten
GS70328SJ-8I Datasheet, Funktion
SOJ, TSOP
Commercial Temp
Industrial Temp
32K x 8
256Kb Asynchronous SRAM
GS70328SJ/TS
7, 8, 10, 12, 15 ns
3.3 V VDD
Corner VDD and VSS
Features
• Fast access time: 7, 8, 10, 12, 15 ns
• 75/65/50/50/50 mA at max cycle rate
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
SJ: 300 mil, 28-pin SOJ package
TS: 8 mm x 13.4 mm, 28-pin TSOP Type I package
Pin Descriptions
Symbol
A0–A14
DQ1–DQ8
CE
WE
Description
The GS70328 is a high speed CMOS static RAM organized as
32,763 words by 8 bits. Static design eliminates the need for
external clocks or timing strobes. The GS70328 operates on a
single 3.3 V power supply, and all inputs and outputs are TTL-
compatible. The GS70328 is available in 300 mil, 28-pin SOJ
and 8 x 13.4 mm2, 28-pin TSOP Type-I packages.
OE
VDD
VSS
NC
Pin Configuration
Top view
A14 1
A12 2
28 VDD
27 WE
A7 3
26 A13
A6 4
25
A5 5
24
A4 6 28-pin 23
A3 7
22
300 mil
A2 8
21
A1 9 SOJ 20
A0 10
19
DQ1 11
18
DQ2 12
17
A8
A9
A11
OE
A10
CE
DQ8
DQ7
DQ6
OE 1
A11 2
A9 3
A8 4
A13 5
WE 6
VDD 7
A14 8
A12 9
A7 10
A6 11
A5 12
A4 13
A3 14
DQ3 13
16 DQ5
VSS 14
15 DQ4
Description
Address input
Data input/output
Chip enable input
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
28- pin
8 x 13.4 TSOP I
28 A10
27 CE
26 DQ8
25 DQ7
24 DQ6
23 DQ5
22 DQ4
21 VSS
20 DQ3
19 DQ2
18 DQ1
17 A0
16 A1
15 A2
Rev: 1.10 10/2002
1/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.






GS70328SJ-8I Datasheet, Funktion
Read Cycle 1: CE = OE = VIL, WE = VIH
Address
Data Out
tOH
Previous Data
tRC
tAA
Read Cycle 2: WE = VIH
Address
CE
OE
Data Out
tRC
tAA
tAC
tLZ
tOLZ
High impedance
tOE
Data valid
tHZ
tOHZ
DATA VALID
GS70328SJ/TS
Rev: 1.10 10/2002
6/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.

6 Page









GS70328SJ-8I pdf, datenblatt
GS70328SJ/TS
Revision History
Rev. Code: Old;
New
1.03 8/1999;
1.04 11/1999
GS70328Rev1.04 12/1999KRev
1.05 2/2000L
Rev 1.05 2/2000L; Rev1.06 6/2000
Rev1.06; Rev1.07
70328_r1_07; 70328_r1_08
70328_r1_08; 70328_r1_09
70328_r1_09; 70328_r1_10
Types of Changes
Format or Content
Page #/Revisions/Reason
Content
• Added 12ns speed bin information to 70328 datasheet.
Format/Content
• GSI Logo
Content
Format/Content
Content
Content
Content
• Nominal value for HD on the TSOP-I 28-pin package changed
to 13.4
• Updated format to conform to Tech Pubs standards
• Corrected errors in both case diagrams
• Added 12 ns reference to Parameter column in
Recommended Operating Conditions table on page 3
• Added 15 ns references to entire document
• Removed 6 ns speed bin from entire document
Rev: 1.10 10/2002
12/12
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, Giga Semiconductor, Inc.

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