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PDF GP2021 Data sheet ( Hoja de datos )
| Número de pieza | GP2021 | |
| Descripción | GPS 12 channel Correlator Advance Information | |
| Fabricantes | Mitel Networks Corporation | |
| Logotipo |  |
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GP2021
GPS 12 channel Correlator
Advance Information
DS4077 - 2.6 July 1996
The GP2021 is a 12 channel C/A code baseband
correlator for use in NAVSTAR GPS and GLONASS satellite
navigation receivers. The GP2021 complements the GP2015
and GP2010 C/A code RF downconverters available from
Mitel Semiconductor.
The GP2021 is compatible with most 16 bit and 32 bit
microprocessors, especially those from Motorola and Intel,
with additional on–chip support for the ARM60 32 bit RISC
processor. When the ARM60 is used, the on–chip memory
management functions allow implementation of a full GPS
receiver with minimal external logic.
The GP2021 allows individual channel de–activation, for
systems not requiring full 12 channel operation, to save power
and processor loading. Receiver power may be further
conserved by reducing the supply voltage to 2.2V under
battery backup. Although all system functions are disabled,
the 32.768kHz oscillator and Real Time Clock are maintained
for the microprocessor to estimate satellite visibility at power
on to reduce signal acquisition time.
A development system called the GPS Architect is
available as a basis for receiver design using the GP2021 and
associated products.
FEATURES
s 12 Fully Independent Correlation Channels
s 1PPS UTC Aligned Timing Output
s On–Chip Dual UART and Real Time Clock
s Compatible with most 16 and 32 bit Microprocessors
s Memory Control Logic for ARM60 Microprocessor
s Low Voltage, Low Current Power–Down Mode
s Power Dissipation 150mW Typical
s Compatible with GP2015 and GP2010 RF Front Ends
s Battery Backup Voltage 2.2V (min)
APPLICATIONS
s GPS Navigation Systems
s High Integrity Combined GPS–GLONASS Receivers
s GPS Geodetic Receivers
s Time Transfer Receivers
ORDERING INFORMATION
GP2021/IG/GQ1R
RELATED PRODUCTS
PART
DESCRIPTION
GP2015
GP2010
DW9255
P60ARM
GPS Architect
GPS Receiver RF Front End
– TQFP 48 package
GlPS Receiver RF Front End
– PQFP 44 package
35.42MHz SAW Filter
32 bit RISC Microprocessor
GPS 12 Channel
Receiver Development System
DATASHEET
REFERENCE
DS4374
DS4056
DS3861
DS3553
DS4004
GP2021
PIN 1 IDENT
PIN 1
Fig.1 Pin connections - top view
GQ80
PIN DESCRIPTION
1 MULTI_FN_IO
2 POWER _GOOD
3 NRESET_OP
4 NARMSYS
5 XIN
6 XOUT
7 TXA
8 TXB
9 RXA
10 RXB
11 NROM / NC
12 NEEPROM / NC
13 NSPARE_CS / NC
14 VDD
15 VSS
16 NRAM / BC
17 NW0 / NC
18 NW1 / NC
19 NW2 / NC
20 NW3 / NC
21 NRD / NC
22 ARM_ALE / NC
23 DBE / NC
24 ACCUM_INT
25 MEAS_INT
26 NBW / WRPROG
27 NMREQ / DISCIP2
28 NOPC / NINTELMOT
29 NRW / DISCIP3
30 MCLK / NC
31 ABORT / MICRO_CLK
32 DISCIO
33 A22 / READ
34 VDD
35 VSS
36 A21 / NCS
37 A20 / WREN
38 A9
39 A8
40 A7
PIN DESCRIPTION
41 A6
42 A5
43 A4
44 A3
45 A2
46 A1 / ALE_IP
47 A0 / NRESET_IP
48 D0
49 D1
50 D2
51 D3
52 D4
53 D5
54 D6
55 VDD
56 VSS
57 D7
58 D8
59 D9
60 D10
61 D11
62 D12
63 D13
64 D14
65 D15
66 PLL_LOCK
67 VDD
68 DISCOP
69 V
SS
70 CLK_T
71 CLK_I
72 VSS
73 SAMPCLK
74 VDD
75 NBRAM / DISCIP4
76 SIGN0
77 MAG1
78 SIGN1
79 MAG1
80 DISCIP1
1 page  
GP2021
Pin No
Signal Name Type
2
POWER_GOOD
I
3 NRESET_OP O
4
NARMSYS
I
5 XIN I
6
XOUT
O
7 TXA O
8 TXB O
9
RXA
1
10
RXB
I
11
NROM / NC
O
12 NEEPROM / NC O
13 NSPARE_CS / NC O
16
NRAM / NC
O
17
NW0 / NC
O
18
NW1 / NC
O
19
NW2 / NC
O
20
NW3 / NC
O
21
NRD / NC
O
22
ARM_ALE / NC
O
23
DBE / NC
O
24
ACCUM_INT
O
25
MEAS_INT
O
26
NBW / WRPROG
I
27 NMREQ / DISCIP2 I
28 NOPC / NINTELMOT I
29
NRW / DISCIP3
I
30
MCLK / NC
O
Description ARM System Mode
Description Standard Interface
Mode
Power Monitor input. High for normal operation. Low forces the GP2021 into
Power Down mode.
System Reset output (Active Low). Lasts for 4 MICRO_CLK cycles after all reset
conditions have cleared.
Processor Mode Selection input. When Low, this input selects ARM System
mode. When High, Standard Interface mode is selected.
Crystal input connection to Real Time Clock.
Crystal output connection from Real Time Clock.
Transmit Data output from Channel A of the Dual UART.
Transmit Data output from Channel B of the Dual UART.
Receive Data input to Channel A of the Dual UART. This pin acts as a master clock
input in Digital System Test mode.
Receive Data input to Channel B of the Dual UART. This pin acts as the Real Time
Clock reset in Digital System Test mode.
ROM Chip Select output (Active Low).
Unused output. (Do not connect.)
EEPROM Chip Select output (Active Low) Unused output. (Do not connect.)
Spare Chip Select output (Active Low).
Unused output. (Do not connect.)
RAM Chip Select output (Active Low).
Unused output. (Do not connect.)
Byte 0 Write Strobe output (Active Low). Unused output. (Do not connect.)
Byte 1 Write Strobe output (Active Low). Unused output. (Do not connect.)
Byte 2 Write Strobe output (Active Low). Unused output. (Do not connect.)
Byte 3 Write Strobe output (Active Low). Unused output. (Do not connect.)
Read Data Strobe output (Active Low).
Unused output. (Do not connect.)
ALE output to the microprocessor
(Active High). Controls the transparent
latches at the microprocessor address
outputs.
Unused output. (Do not connect.)
Data Bus Enable output to the
microprocessor. When Low, places the
microprocessor data bus drivers in a
high impedance state.
Unused output. (Do not connect.)
A free running interrupt to the microprocessor. It allows control of data transfer
between the accumulators in the correlator and the microprocessor. It is active
Low when configured for ARM System mode or Motorola mode and is active High
in Intel mode.
An interrupt to the microprocessor. It allows control of measurement data transfer
between the correlator and the microprocessor. It is active Low when configured
for ARM System mode or Motorola mode and is active High in Intel mode.
Byte/Word input from the
microprocessor. Low indicates a byte
transfer, and High a word transfer.
Write–Read Program input. In Intel
mode, High selects 486 style
interface and Low 186 style.
Unused in Motorola mode
Memory Request input from the
microprocessor. Low indicates that the
microprocessor requires a memory
access during the following cycle.
Multi–purpose discrete input.
Opcode fetch input from the
microprocessor. Low indicates that an
instruction is being fetched and High
that data is being transferred.
High selects Motorola mode and
Low Intel mode.
Read/Write Select input from the
microprocessor. Low indicates a read
cycle and High a write cycle.
Multi–purpose discrete input.
Microprocessor Clock output
(nominally 20MHz). Its phases can be
stretched under control of the
Microprocessor Interface.
Unused output. (Do not connect.)
5
5 Page 
GP2021
Epoch Counter
The Epoch Counters keep track of the number of code
periods over a 1 second interval. This is represented by a 5 bit
word for the number of 1 ms integration periods (0 to 19), plus
a 6 bit word containing the number of 20 ms counts (0 to 49).
The Epoch Counters can be pre–loaded to synchronise them
to the data stream coming from the satellite. This value will be
transferred immediately to the counter when in Update mode,
or after the next TIC if in PRESET Mode.
The Epoch Counter values are latched on each TIC into the
CHx_EPOCH register. In addition the instantaneous values
are available from the CHx_EPOCH_CHECK register.
PERIPHERAL FUNCTIONS
The following section describes the Dual UART, Real
Time Clock and Watchdog, Power and Reset Control and
Discrete I/O blocks.
Dual UART
A Dual UART is included for serial communications. It has
2 identical blocks, UART_A and UART_B, each containing
separate transmit and receive channels. The parity and
separate transmit and receive baud rate can be configured
independently for each UART. Each uses a polled processor
interface and each transmit and receive channel has an 8 byte
deep FIFO.
For further information on the UART registers refer to the
Detailed Description of Registers and the GP2021 Register
Map.
A typical serial data stream is shown in Fig. 6. The Parity
bit is optional and if no parity is selected the time slot for it is
removed from the data stream and the Stop bit follows
immediately after the last data bit in both transmit and receive
directions. Note that the LSB is always preceded by a Start bit.
Table 3 shows possible UART configurations.
Start
First
D8
LSB
D9 D10 D11 D12 D13 D14 D15
P Stop
MSB Parity Last
(optional)
Fig. 6 Serial Data waveform
Parameter
Value
Start bits
Data bits
Stop bits
1 bit Low
8 bits Logic 0 = Low
Logic 1 = High
1 bit High
Parity
Flow control
Transmit FIFO depth
Odd/Even/None
None
8 bytes
Receive FIFO depth
8 bytes
FIFO speed
Data rate
Transmit FIFO write rate and Receive FIFO read rate maximum is one byte per 230ns.
The maximum buffer through delay is 2 µ s.
300, 600,1.2k, 2.4k, 4.8k, 9.6k, 19.2k, 38.4k and 76.8k baud. Transmit and Receive
rates individu-ally configured.
Table 3 UART Functionality
Receiver
The incoming data streams on RXA, RXB are sampled by
a clock at nominally 20 times the data rate, to search for an
incoming Start bit. Once the receiver is synchronised to the
data stream, each data bit is sampled only at its nominal centre
to avoid errors due to slow or noisy bit edges. The receiver will
resynchronise to each Start bit to prevent the accumulation of
phase errors.
Only valid data (having correct Start, Stop and Parity bits)
will be stored in the receiver FIFO. If a received word contains
a parity or framing (Start/Stop bit) error, the appropriate flag bit
will be set in the status register. If too many valid data words
are received for the FIFO to hold, the excess will not be written
into the FIFO, and an Overflow bit will be set in the status
register. When receiving a continuous transmission, the Start
bit of one word will follow immediately after the Stop bit of the
preceding word. At lower word rates, a High is expected
between words. The receiver will accept data with a baud rate
error of up to ±1%.
Transmitter
Data is transmitted on pins TXA and TXB. In continuous
transmission, the Start bit of one word will follow immediately
after the Stop bit of the preceding word. At lower word rates,
a High is sent between words.
If too many data words are written by the microprocessor
to the UART for the transmitter FIFO to hold, the excess will not
be stored. The UART will resume normal operation as soon as
space becomes available. To avoid data loss, the software
should limit the transmit data rate by either: keeping track of
the number of bytes sent and the time to transmit them, or
should read the Status register and stop writing when the Full
bit is set.
11
11 Page | ||
| Páginas | Total 62 Páginas | |
| PDF Descargar | [ Datasheet GP2021.PDF ] | |
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