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PDF GM82C765B Data sheet ( Hoja de datos )
| Número de pieza | GM82C765B | |
| Descripción | FLOPPY DISK SUBSYSTEM CONTROLLER | |
| Fabricantes | Hynix Semiconductor | |
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GM82C765B
GM82C765B
FLOPPY DISK SUBSYSTEM CONTROLLER
General Description
The GM82C765B is a CMOS LSI device which interfaces a host
microprocessor to the floppy disk drive. It integrates the function of the
Formatter/Controller, Data Separator. Write Precompensation, Data rate
selection, Clock Generation, High Current Output Drivers, and TTL
compatible Schmitt Trigger Receivers. The GM82C765B consists of a
microprocessor interface, a microsequencer and a disk drive interface.
The host microprocessor interface of the GM82C765B supports a
12MHz, 286 microprocessor bus without the use of wait states. All inputs
within host microprocessor are Schmitt triggers, except for the data bus,
XTAL, and the host output sink 12mA.
Output drive capability is 20 LSTTL load, allowing direct
interconnection to bus structures without the use of buffers or transceivers.
On the disk drive interface, the GM82C765B includes data seperation that
has been designed to address high performance error rate on floppy disk
drives, and contains all the necessary logic to achieve classical 2nd order,
type2, phase locked loop performance. Write precompensation is included,
in addition to the usual formatting, encoding, decoding, step motor control,
and status sensing functions For PC/XT and PC/AT applications, the
device provides qualification of interrupt and DMA requests.
The disk drive interface of the GM82C765B connects directly to up to
four drives. All drive-related inputs are Schmitt triggers and the drive
outputs are open drain, and sink 48 mA.
The GM82C765B uses two clock inputs which provide the necessary
signals for internal timing. A 16MHz oscillator controls the data rate of
500, 250 and 125Kbits/sec, while a 9.6MHz oscillator controls the
300Kbit/sec data rate used in PC/AT designs.
The two XTAL oscillator circuits may be used for the 44-pin PLCC
package, while TTL clock inputs must be provided when using the 40-pin
DIP package.
In the PLCC version of the GM82C765B pins 17 and 40, which were
not utilized in DIP version of the GM82C765B, became DCHGEN (Disk
Change Enable) and DCHG (Disk Change) respectively. Both are active
LOW. DCHGEN is offered as an option for those designs that used the
original GM82C765B part where DCHG did not exist as direct into the
chip.
The GM82C765B has eight internal Registers. The 8 bit main status
register contains status information of the GM82C765B and may be
accessed any time. Another four status register under system control also
give various status and error information. The Control Register provides
support logic that latches the two LSBs used to select the desired data rate
that controls internal clock generation. The Operations Register replaces
the standard latched port used in floppy subsystem.
Features
∗ IBM PC compatible format
(single and double density)
– Floppy disk control and
operations on chip
– In PC AT mode, provides required
signal qualification DMA channel
– BIOS compatible and dual speed
Spindle Drive support
∗ Integrates Formatter/Controller/Data
Separation, Write Precompensation,
Data rate Selection, Clock
Generation, and drive interface
Drivers and Receivers into one chip
∗ Multisector and Multitrack transfer
capability.
∗ Direct Floppy Disk Drive interface
with no buffers needed
– 48mA sink output drivers
– Schmitt trigger Line Receivers
∗ Enhanced Host Interface:
– Supports 12MHz, 286 u-processor
– Capable of driving 20 LSTTL
Load
∗ Address mark detection circuitary
internal to Floppy Disk Controller
∗ On chip Clock Generation
Two TTL Clock Inputs for 40-DIP
∗ Two XTAL oscillator circuits for
44-Quad, PLCC
∗ User programmable Track Stepping
Rate and Head load/unload time
∗ Drivers up to four Floppy or micro
Floppy Disk Drives
∗ Data transfer DMA or non-DMA
mode
∗ Parallel seek operations on up to
four Drives
∗ Internal power up reset circuitry
∗ READ/WRITE access compatible
register with 8 or 12MHz 286
microprocessor with 0 wait states.
∗ DMA timing corrected.
∗ LOW POWER CMOS, +5V SUPPLY
1
1 page  
GM82C765B
PIN NO MNEMOMICSIGNAL NAME I/O
DIP PLCC
FUNCTION
34 37
MO2 ,
DS4
MOTOR ON 2 O This HCD output, when active low, is MOTOR ON
DRIVE SELECT4 HCD enable for disk drive #2, in PC AT mode. This signal
comes from the Operations Reg. In the Base or Special
mode, this output is #4 of the four decoded Unit
Selects as specified in the device command syntax
35 38
HDL
HEAD
O This HCD output, when active low, causes the head to
LOADED
HCD be loaded against the media in the selected drive.
36 39
RWC
REDUCED
O This HCD output, when active los, causes a
RPM
WRITE
CURRENT,
HCD REDUCED WRITE CURRENT when bit density is
increased toward the inner tracks, becoming active
REVOLUTIONS
when tracks>28 are accessed. This condition is valid
PER MINUTE
for Base or Special mode, and is indicative of when
write precompensation is necessary. In the PC AT
mode, this signal will be active when CR0=1
40 DCHG DISK
I This ST input senses status from the drive, indicating
CHANGE
ST active low that drive door is open or that the diskette
has possibly changed since last drive selection.
37 41
WP
WRITE
I This Schmitt Trigger (ST) input senses status from the
PROTECTED ST disk drive, indicating active low when a diskette is
WRITE PROTECTED
38 42
TR00
TRACK 00
I This ST input senses status from disk drive indicating
ST active low when the head is positioned over the
outermost track, TRACK 00
39 43
IDX
INDEX
I This ST input senses status from the disk drive,
ST indicating active low when the head is positioned over
the beginning of a track marked by an index hole.
40 44 VCC
+5V DC
Input power supply.
Note: N – NORMAL INPUT, OUTPUT PAD
BI – BIDIRECTIONAL I/O PAD
ST – SCHMITT TRIGGER INPUT PAD
HCD – OPEN DRAIN HIGH CURRENT DRIVE OUTPUT PAD
5
5 Page 
3. ARCHITECTURE
The GM82C765B Floppy Disk Subsystem
Controller is a CMOS LSI device that provides
all the needed functionality between the host
u-processor peripheral Bus and the cable
Connec-tor to the Floppy Disk Drive. This CHIP
in-tegrates; Formatter/Controller Data Separation,
Write Precompensation, Data rate Seletion,
Clock generation, Drive interface drivers and
receivers.
GM82C765B
HOST INTERFACE
The host interface is the host microprocessor
peripheral bus. This bus is composed of eight
control signals and eight data signals. In the
special or PC AT modes, IRQ and DMA request
are tri-stated and qualified enable, internally
provided by the operations register. The data bus,
DMA, and IRQ outputs are designed to handle 20
LS-TTL loading.
8 Bit
DATA
BUS
CONTROL
REGISTER
MASTER
STATUS REG
DATA
REGISTER
OPERATION
REGISTER
DRV
RD
WR
CS
A0
DACK
TC
DMA
IRQ
LDCR
LDOR
HOST
INTERFACE
CLK1
CLK2
CRYSTAL
OSc×2
8 Bit INTERNAL DATA BUS
CLOCK
AND
TIMING
GENERATOR
MCLK
01
02
WCLK
SCLK
ALU
MS
TIMER
SATE
MACHINE
RAM
24 × 8
INSTRUCTION
DECODE
PROGRAM
COUNTER
FLAG
LOGIC
ROM
1KÏ16
DISK
INTERFACE
CONTROL
REGISTER
HS
HDL
STEP
DIRC
RWC
DS1 − 4
TROO
IDX
WP
DCHG *
DIGITAL DATA
SEPARATOR
DATA ENCODER
DECODER
CRC GENERATOR
WRITE
PRECOMPENSATION
RDD
WE
WD
PCVAL
PLCC version of GM82C765B only
Fig 1. GM82C765B Internal Block Diagram
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GM82C765B.PDF ] | |
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