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GM76U256CLEFW Schematic ( PDF Datasheet ) - Hynix Semiconductor

Teilenummer GM76U256CLEFW
Beschreibung 32K x8 bit 3.0V Low Power CMOS slow SRAM
Hersteller Hynix Semiconductor
Logo Hynix Semiconductor Logo 




Gesamt 11 Seiten
GM76U256CLEFW Datasheet, Funktion
Document Title
32K x8 bit 3.0V Low Power CMOS slow SRAM
Revision History
Revision No History
00 Revision History Insert
Revised
- Datasheet format change
- PDIP package type insert
- Pin configuration change
01 Marking Information Add
Revised
- AC Test Condition Add : 5pF Test Load
02 Changed Logo
- HYUNDAI -> hynix
GM76U256C Series
32Kx8bit CMOS SRAM
Draft Date
Jul.08.2000
Remark
Final
Dec.04.2000 Final
Apr.30.2001 Final
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 02 / Apr. 2001
Hynix Semiconductor






GM76U256CLEFW Datasheet, Funktion
TIMING DIAGRAM
READ CYCLE 1
ADDR
OE
CS
Data
Out
High-Z
tRC
tAA
tOE
tOLZ
tACS
tCLZ
GM76U256C Series
tOH
tOHZ
tCHZ
Data Valid
Note(READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and arenot
referenced to output voltage levels.
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given device
and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
ADDR
Data
Out
tAA
tOH
Previous Data
tRC
Data Valid
tOH
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS= VIL.
3. /OE =VIL.
Rev 02 / Apr. 2001
5

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