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GM71V17403CL-5 Schematic ( PDF Datasheet ) - Hynix Semiconductor

Teilenummer GM71V17403CL-5
Beschreibung 4/194/304 WORDS x 4 BIT CMOS DYNAMIC RAM
Hersteller Hynix Semiconductor
Logo Hynix Semiconductor Logo 




Gesamt 10 Seiten
GM71V17403CL-5 Datasheet, Funktion
Description
The GM71V(S)17403C/CL is the new
generation dynamic RAM organized 4,194,304
words x 4 bit. GM71V(S)17403C/CL has
realized higher density, higher performance and
various functions by utilizing advanced CMOS
process technology. The GM71V(S)17403C/CL
offers Extended Data Out (EDO) Page Mode as
a high speed access mode. Multiplexed address
inputs permit the GM71V(S)17403C/CL to be
packaged in a standard 300 mil 24(26) pin SOJ,
and a standard 300 mil 24(26) pin plastic TSOP
II. The package size provides high system bit
densities and is compatible with widely
available automated testing and insertion
equipment. System oriented features include
single power supply 3.3V +/- 0.3V tolerance,
direct interfacing capability with high
performance logic families such as Schottky
TTL.
Pin Configuration
24(26) SOJ
GM71V17403C
GM71VS17403CL
4,194,304 WORDS x 4 BIT
CMOS DYNAMIC RAM
Features
* 4,194,304 Words x 4 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (3.3V +/- 0.3V)
* Fast Access Time & Cycle Time
(Unit: ns)
t t t tRAC CAC RC
HPC
GM71V(S)17403C/CL-5
GM71V(S)17403C/CL-6
GM71V(S)17403C/CL-7
50 13 84
60 15 104
70 18 124
20
25
30
* Low Power
Active : 432/369/360mW (MAX)
Standby : 7.2mW (CMOS level : MAX)
: 0.36mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
*All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Backup Operation (L-version)
* Test Function : 16bit parallel test mode
24(26) TSOP II
VCC 1
I/O1 2
I/O2 3
WE 4
RAS 5
NC 6
A10 8
A0 9
A1 10
A2 11
A3 12
VCC 13
26 VSS
25 I/O4
24 I/O3
23 CAS
22 OE
21 A9
VCC 1
I/O1 2
I/O2 3
WE 4
RAS 5
A11 6
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
A10 8
A0 9
A1 10
A2 11
A3 12
VCC 13
(Top View)
26 VSS
25 I/O4
24 I/O3
23 CAS
22 OE
21 A9
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
Rev 0.1 / Apr’01






GM71V17403CL-5 Datasheet, Funktion
Write Cycle
Symbol
Parameter
tWCS
tWCH
tWP
tRWL
tCWL
tDS
tDH
Write Command Setup Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
Data-in Hold Time
Read- Modify-Write Cycle
Symbol
Parameter
tRWC
tRWD
tCWD
tAWD
tOEH
Read-Modify-Write Cycle Time
RAS to WE Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
OE Hold Time from WE
GM71V17403C
GM71VS17403CL
GM71V(S)17403 GM71V(S)17403 GM71V(S)17403
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
0-
0-
0-
ns
8 - 10 - 13 - ns
8 - 10 - 10 - ns
8 - 10 - 13 - ns
8 - 10 - 13 - ns
0-
0- 0-
ns
8 - 10 - 13 - ns
Note
14
15
15
GM71V(S)17403 GM71V(S)17403 GM71V(S)17403
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
111 - 136 - 161 - ns
67 - 79 - 92 - ns
30 - 34 - 40 - ns
42 - 49 - 57 - ns
13 - 15 - 18 - ns
Note
14
14
14
Refresh Cycle
Symbol
Parameter
tCSR CAS Setup Time
(CAS-before-RAS Refresh Cycle)
tCHR CAS Hold Time
(CAS-before-RAS Refresh Cycle)
tWRP WE Setup Time
(CAS-before-RAS Refresh Cycle)
tWRH WE Hold Time
(CAS-before-RAS Refresh Cycle)
tRPC RAS Precharge to CAS Hold Time
GM71V(S)17403 GM71V(S)17403 GM71V(S)17403
C/CL-5
C/CL-6
C/CL-7
Min Max Min Max Min Max
Unit
Note
5-
5-
5-
ns
8 - 10 - 10 - ns
0-
0-
0-
ns
10 - 10 - 10 -
5-
5-
5-
ns
ns
Rev 0.1 / Apr’01

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