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PDF CCD3041 Data sheet ( Hoja de datos )
| Número de pieza | CCD3041 | |
| Descripción | Front-Illuminated 2K x 2K Full Frame CCD Image Sensor | |
| Fabricantes | Fairchild Imaging | |
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CCD 3041
Front-Illuminated 2K x 2K
Full Frame CCD Image Sensor
FEATURES
• 2048 x 2048 Full Frame CCD
• 15 μm x 15 μm Pixel
• 30.72 mm x 30.72 mm Image Area
• 100% Fill Factor
• Multi-Pinned Phase (MPP) Operation
• Readout Noise Less Than 3 e- at 50kHz
• Four Low Noise Output Amplifiers
• Three Phase Buried Channel CCD
GENERAL DESCRIPTION
The CCD 3041 is a 2048(H) x 2048(V) solid state Charge
Coupled Device (CCD) full frame sensor. The CCD is intended for
advanced scientific, aerospace, industrial, and medical imaging
applications. The CCD 3041 active area is organized as an array
of 2048 horizontal by 2048 vertical imaging elements. The pixel
pitch is 15μm with a 100% fill factor. For dark reference, each
readout line is preceded by 16 dark pixels. The imager is
available in front- or back-illuminated configurations; however, this
data sheet is for the front-illuminated configuration only. A split
shift register design architecture has been adopted to
accommodate high data rates by allowing the entire active pixel
array to be read out simultaneously from all four output ports. In
addition to 4 port readout, the standard package provides the
ability to read out the image data from two output ports, located
on the same side of the array. A simple modification allows the
ability to read out the entire image frame from a single output port
only, in order to simplify the drive electronics requirements.
A single-stage source follower output amplifier design has been
selected for low noise performance. The readout noise floor is
typically better than 3 e- at a pixel rate of 50 kHz. Each output
amplifier is capable of operating at up to 3 MHz with less than 20
e- nominal read noise.
The CCD 3041 is mounted in a custom ceramic package for
improved flatness uniformity and minimized mass. The PGA
package is 36.8 x 45.7 mm with 46 pins.
FUNCTIONAL DESCRIPTION
The key functional elements are described next, and are shown in
the block diagram:
Image Sensing Elements: The CCD photo-sensitive elements
are made up of contiguous pixels with no voids or inactive areas.
In addition to sensing light, these elements are used to shift
image charge vertically. The full frame architecture requires that
the device be mechanically shuttered during readout.
Vertical Charge Shifting: The architecture of the CCD 3041
provides video information as a sequential readout of 2048 lines,
each containing 2048 photosensitive elements (in 1x1 mode,
using a single output). At the end of the integration period, the
ΦV1, ΦV2, and ΦV3 gates are clocked to transfer charge vertically
through the CCD array and to the horizontal readout register.
Vertical columns are separated by channel stop regions to confine
charge horizontally. The Vertical Transfer Gate (ΦVTG) is the
final array gate before charge is transferred to the serial horizontal
shift registers. For simplified operation ΦVTG may be tied to ΦV3.
The imaging area is electrically divided into four quadrants. Each
1024 x 1024 segment may be clocked independently or combined
as required. Horizontal serial registers along the top and bottom
permit simultaneous readout of the upper and lower halves. The
CCD 3041 also may be clocked such that the full array is read out
of either the upper or the lower serial registers.
Horizontal Charge Shifting: ΦH1, ΦH2, and ΦH3 are polysilicon
gates used to transfer charge horizontally to the output amplifiers.
The pixels in the horizontal registers are twice the size of the
photosites to allow vertical charge binning, and a summing well is
also provided to support horizontal charge binning. The array can
be read out normally at 2K(H) x 2K(V) full resolution, as a 2K(H) x
1K(V), or 1K(H) x 1K(V). The horizontal shift registers are bi-
directional so that the image frame may be read out through a
single, or two amplifiers per serial register.
The transfer of charge into the horizontal registers follows the
vertical charge transport sequence. These registers contain 16
additional register cells between the first pixel of each line and the
output amplifier. (Note that the summing gate is part of the last
prescan pixel.) The output of these pixels contains no signals and
may be used as a dark level reference.
The last clocked gate in the horizontal registers, ΦSG, can be
used to combine the signal charge of the pixels in the horizontal
shift registers. This gate requires its own clock, which may be tied
to ΦH1 for normal full resolution readout. The output video is
available following the high to low transition of ΦTG.
After the pixel has been sampled, the reset transistor, clocked
appropriately with ΦR, resets the sense node potential to the level
set by VRD.
1801 McCarthy Blvd.• Milpitas CA 95035 • (800) 325-6975 • Fax (408) 435-7352 • www.fairchildimaging.com • Rev C • 1 of 10
1 page  
Multi-Pinned Phase: MPP is a CCD technology which
significantly reduces the dark current generation rate. CCDs are
endowed with this capability by the addition of an ion implant step
during the semiconductor manufacturing process.
This implant creates a built-in potential barrier in each pixel, which
allows charge integration to be performed with all of the vertical
clocks biased at their Low levels (-8V). Under these conditions,
the surface potential of the CCD is pinned at 0V, and the holes
released by the neighboring p+ channel stops recombine with the
electrons that are generated by surface defects which effectively
neutralize the surface dark current.
While MPP operation significantly reduces the dark current of the
CCD, a drawback of the MPP mode is reduced full well capacity.
The potential barrier created by MPP implant does not hold as
much charge as the normal buried channel operating mode which
stores charge under one of the vertical gates biased high during
integration. The CCD 3041 fabrication process has been
optimized to maximize the charge capacity in MPP mode.
DEFINITION OF TERMS
Charge-Coupled Device: A charge-coupled device image sensor
is capable of converting incident light photons into discrete
packets of electron charge confined in individual pixels, then
transfer the signal charge by sequential clocking of an array of
gates to on-chip output amplifiers which produce the video output
signals.
Vertical Transport Clocks ΦV1, ΦV2, and ΦV3: The clock
signals applied to the vertical transport registers to move signal
charge from one pixel to the next.
Vertical Transfer Gate ΦVTG: The gate structure located
adjacent to the last row of photosites and the horizontal transport
registers. The charge packets accumulated in the photosites are
shifted vertically across the array, then when they reach the last
row of photosites, the signal charge is transferred to the serial
register by appropriate clocking of the vertical transfer gate.
Proper timing of the ΦVTG gate allows the vertical signal charges
to be combined or binned.
Horizontal Transport Clocks ΦH1, ΦH2, ΦH3: The clock signals
applied to the horizontal transport registers to move signal charge
from one pixel to the next.
Reset Clock ΦR: The clock applied to the reset transistor of the
output amplifier.
Dynamic Range: The ratio of the pixel full well and the RMS
noise floor in the dark. Dynamic range is typically expressed in
dB.
Saturation Exposure: The minimum exposure level that
produces an output signal corresponding to the maximum
photosite charge capacity. Exposure is equal to the product of
light intensity and integration time.
Responsivity: The output signal voltage per unit of exposure.
Spectral Response Range: The spectral band over which the
response per unit of radiant power is more than 10% of the peak
response.
Photo-Response Non-Uniformity: The difference of the
response levels between the most and the least sensitive regions
under uniform illumination (excluding blemished elements)
expressed as a percentage of the average response.
Dark Signal: The output signal caused by thermally generated
electrons. Dark signal is a linear function of integration time, and
varies exponentially as a function of the chip temperature.
Pixel: Picture element or sensor element (also called
photoelement or photosite).
DEVICE HANDLING PRECAUTIONS
Due to the negative bias conditions necessary for proper
operation, the CCD3041 is not equipped with built-in ESD
protection circuitry. Strict ESD procedures and proper handling
precautions must be performed to avoid accidental damage to the
devices. The warranty does not apply to ESD damaged devices.
• Always store the devices with the shorting pins that are
shipped with the devices securely attached to all of the pins.
• Never insert or remove the device from a live socket or
operating camera. Turn off all electrical power first.
• Test stations must be specifically designed to minimize static
charge build-up, including ionizing air blowers, and grounded
floor mats.
• The relative humidity level in the working environment must
be controlled between 40% - 60%.
• Never handle the devices without proper personal ESD
protection items such as tested grounding straps, electrically
conductive gloves or finger cots, ESD safe smocks,
conductive shoe straps are also desirable.
ABSOLUTE MAXIMUM RATINGS
Storage temperature range .................... -50 ºC to +75 ºC
Operating temperature range ................. -100 ºC to +40 ºC
1801 McCarthy Blvd.• Milpitas CA 95035 • (800) 325-6975 • Fax (408) 435-7352 • www.fairchildimaging.com • Rev C • 5 of 10
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CCD3041.PDF ] | |
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