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CCD8091 Schematic ( PDF Datasheet ) - Fairchild Imaging

Teilenummer CCD8091
Beschreibung 9K x 128 Element Delay and Integration Sensor
Hersteller Fairchild Imaging
Logo Fairchild Imaging Logo 




Gesamt 24 Seiten
CCD8091 Datasheet, Funktion
CCD8091
9K x 128 Element
TDI – Time, Delay and Integration Sensor
FEATURES
9216 pixels per line
Number of TDI stages electronically
selectable: {4, 8, 16, 32, 64, 96, 128}
Bi-directional TDI (shift up or down)
6 outputs — each capable of 20MHz data
rate — 160MHz total data rate
100% fill factor
8.75µm x 8.75µm pixel size
On-chip binning capability
GENERAL DESCRIPTION
The CCD8091 is a 9216 pixel x 128 line,
high speed TDI sensor. The active imaging
area is organized as 9216 vertical columns
and 128 horizontal TDI rows. The array is
set up for bi-directional operation. There are
identical output registers and amplifiers on
both the top and the bottom of the array.
The outputs to be used (either top or
bottom) are user-selectable and controlled
by the vertical clock timing. In addition, the
exposure level can be controlled by reducing
the number of TDI rows from 128 to 96, 64,
32, 16, 8 or 4. This is also user-selectable
and is accomplished by supplying the
appropriate phasing for the vertical clocks
within each section. For instance, if 64 lines
of TDI were required, the vertical clocks for
lines 65-128 would be connected to a high
potential, which would drain these unused
rows out to the opposite side (unused) of the
array to be dumped into the VOFD drain.
With six outputs, each running at 20MHz,
the CCD8091 can provide a total data rate
of 120MHz enabling the CCD to run at better
than 12kHz line rate. Utilizing Fairchild
Imaging proprietary buried channel CCD
process, the CCD8091 achieves consistent,
superior TDI performance.
The active imaging area is separated from
the six horizontal output registers by 21
isolation rows. These isolation rows are
covered by a metal lightshield to protect
them while charge transfers to the output
registers. Both the active imaging area and
the isolation region utilize 3-phase clocking.
The six horizontal output registers utilize 4-
phase clocking. Special design techniques
have been implemented to maximize charge
transfer efficiency especially at low light
levels. The output amplifier is a 3-stage
source follower configuration. This allows
maximum scale factor (charge to voltage
conversion) and maximum bandwidth.
The CCD8091 is housed in a custom 176
pin (100 mil grid) ceramic PGA package. It
has an AR coated window.
FUNCTIONAL DESCRIPTION
The following functional elements are
illustrated in the block diagram:
Image Sensing Elements: These are
elements of a line of 9216 image sensors
separated by channel stops and covered by
a passivation layer. Incident photons pass
through a transparent polycrystalline silicon
gate structure creating electron hole pairs.
The resulting photoelectrons are collected in
the photosites during the integration period.
The amount of charge accumulated in each
photosite is a linear function of the localized
incident illumination intensity and integration
period.
Transfer Gates: This gate is a structure
adjacent to the row of image sensor
elements. The charge packets accumulated
in the photosites are transferred in parallel
via the transfer gate to the transport shift
1801 McCarthy Blvd.• Milpitas CA 95035 • (800) 325-6975 • Fax (408) 435-7352 • www.fairchildimaging.com • Rev B • 1 of 24






CCD8091 Datasheet, Funktion
CCD8091
9K x 128 Element
TDI—Time, Delay and Integration Sensor
Block Diagram at Pixel Array Vertical Centerline
1 pixel up
(8.75µm)
CL
1 pixel down
(8.75µm)
pixel col. #(x+2)
V3D-T
V1D-T
V2D-T
VSW16-U
V1E-T
V2E-T
V3E-T
V1E-T
V2E-T
V3E-T
V1E-T
V2E-T
V3E-T
V1E-T
V2E-T
VSW32-U
V1F-T
V2F-T
V3F-T
V1F-T
V2F-T
V3F-T
V1F-T
V2F-T
V3F-T
V1F-T
V2F-T
VSW64
V1F-B
V2F-B
V3F-B
V1F-B
V2F-B
V3F-B
V1F-B
V2F-B
V3F-B
V1F-B
V2F-B
VSW32-D
V1E-B
V2E-B
V3E-B
V1E-B
V2E-B
V3E-B
V1E-B
V2E-B
VSW16-D
V1D-B
V2D-B
pixel col. #(x+2)
pixel col. #(x+1)
V3D-T
V1D-T
V2D-T
VSW16-U
V1E-T
V2E-T
V3E-T
V1E-T
V2E-T
V3E-T
V1E-T
V2E-T
V3E-T
V1E-T
V2E-T
VSW32-U
V1F-T
V2F-T
V3F-T
V1F-T
V2F-T
V3F-T
V1F-T
V2F-T
V3F-T
V1F-T
V2F-T
VSW64
V1F-B
V2F-B
V3F-B
V1F-B
V2F-B
V3F-B
V1F-B
V2F-B
V3F-B
V1F-B
V2F-B
VSW32-D
V1E-B
V2E-B
V3E-B
V1E-B
V2E-B
V3E-B
V1E-B
V2E-B
VSW16-D
V1D-B
V2D-B
pixel col. #(x+1)
pixel col. #(x)
V3D-T
V1D-T
V2D-T
VSW16-U
V1E-T
V2E-T
V3E-T
V1E-T
V2E-T
V3E-T
V1E-T
V2E-T
V3E-T
V1E-T
V2E-T
VSW32-U
V1F-T
V2F-T
V3F-T
V1F-T
V2F-T
V3F-T
V1F-T
V2F-T
V3F-T
V1F-T
V2F-T
VSW64
V1F-B
V2F-B
V3F-B
V1F-B
V2F-B
V3F-B
V1F-B
V2F-B
V3F-B
V1F-B
V2F-B
VSW32-D
V1E-B
V2E-B
V3E-B
V1E-B
V2E-B
V3E-B
V1E-B
V2E-B
VSW16-D
V1D-B
V2D-B
pixel col. #(x)
Switch gate to select TDI-16 up (or TDI-112 down)
TDI transfer
Up
16 “low-speed” (~50% duty-cycle clocks) pixel rows
Switch gate to select TDI-32 up (or TDI-96 down)
32 “low-speed” (~50% duty-cycle clocks) pixel rows
Switch gate to select TDI-64 up or TDI-64 down
32 “low-speed” (~50% duty-cycle clocks) pixel rows
Switch gate to select TDI-32 down (or TDI-96 up)
16 “low-speed” (~50% duty-cycle clocks) pixel rows
Down
TDI transfer
Switch gate to select TDI-16 down (or TDI-112 up)
1801 McCarthy Blvd.• Milpitas CA 95035 • (800) 325-6975 • Fax (408) 435-7352 • www.fairchildimaging.com • Rev B • 6 of 24

6 Page









CCD8091 pdf, datenblatt
CCD8091
9K x 128 Element
TDI—Time, Delay and Integration Sensor
CCD8091 Clock Capacitance
Symbol
Parameter
Min Typ Max
Photosite rows: V1, V2, V3: capacitance per pixel row
V1 to VSS
16
V1 to V2
19
V1 to V3
18
Unit
pF
pF
pF
Remarks
V2 to VSS
V2 to V3
24 pF
22 pF
V3 to VSS
22 pF
Isolation and high-speed rows: capacitance per row
V1 to VSS
20 pF
V1 to V2
19 pF
V1 to V3
18 pF
V2 to VSS
V2 to V1 (see above)
V2 to V3
30 pF
22 pF
V3 to VSS
V3 to V1 (see above)
V3 to V2 (see above)
31 pF
Horizontal transport gate and reset gate capacitance per 1536-element output section
H1 90 110 pF
H2 90 110 pF
H3 90 110 pF
H4 110 130 pF
ΦOG
10 pF
ΦR 10 pF
Total for each H-clock includes ~50pF gate-to-gate capacitance, mostly to the nearest neighboring H-gates.
For example, H1 has ~67pF H1-VSS, ~20pF H1-H2, ~30pF H1-H4, and ~3pF H1-H3.
1801 McCarthy Blvd.• Milpitas CA 95035 • (800) 325-6975 • Fax (408) 435-7352 • www.fairchildimaging.com • Rev B • 12 of 24

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