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R196U2-L02 Schematic ( PDF Datasheet ) - CHIMEI Innolux

Teilenummer R196U2-L02
Beschreibung TFT LCD Module
Hersteller CHIMEI Innolux
Logo CHIMEI Innolux Logo 




Gesamt 30 Seiten
R196U2-L02 Datasheet, Funktion
Global LCD Panel Exchange Center
www.panelook.com
PRODUCT SPECIFICATION
ʳ
ϭ Tentative Specificationʳ
ϭ Preliminary Specificationʳ
Ϯ Approval Specification
MODEL NO.: R196U2
SUFFIX: L02
Customer:
APPROVED BY
Name / Title
Note
SIGNATURE
Please return 1 copy for your confirmation with your
signature and comments.
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2011-01-25
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Directorʳ Acceptʳ
Version 2.1
18 January, 2011
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited.
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R196U2-L02 Datasheet, Funktion
Global LCD Panel Exchange Center
www.panelook.com
PRODUCT SPECIFICATION
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
Parameter
Power Supply Voltage
Ripple Voltage
Rush Current
White
Power Supply Current Black
Vertical Stripe
Power Consumption
Magnitude LVDS differential input voltage
LVDS common input voltage
Logic high input voltage
Logic low input voltage
Symbol
Vcc
VRP
IRUSH
-
-
-
PLCD
|Vid|
Vic
VIH
VIL
Min.
11.4
-
-
-
-
-
-
100
1.0
2.64
-
Value
Typ.
12.0
-
-
510
270
460
6.12
-
1.2
-
-
Note (1) The module should be always operated within above ranges.
Note (2) Measurement Conditions:
+12.0V
Q1 2SK1475
FUSE
R1
47K
(High to Low)
(Control Signal)
SW
+15.2V
C1
1uF
Q2
R2
2SK1470
1K
VR1 47K
C2
0.01uF
Ta = 25 ± 2 ºC
Max. Unit Note
12.6 V
-
300 mV
-
3.8 A (2)
612 mA (3)a
324 mA (3)b
552 mA (3)c
7.71 watt
(4)
600 mV
1.4 V
-V
0.66 V
Vcc
C3
(LCD Module Input)
1uF
Version 2.1
18 January, 2011
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited.
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R196U2-L02 pdf, datenblatt
Global LCD Panel Exchange Center
www.panelook.com
PRODUCT SPECIFICATION
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 LVDS Input Signal
J1(Master) : Right side(Front View)
Signal Description (J1)
Pin Name
1 VCC
2 VCC
3 GND
4 GND
5 RXE0-
6 RXE0+
7 GND
8 RXE1-
9 RXE1+
10 GND
11 RXE2-
12 RXE2+
13 GND
14 RXEC-
15 RXEC+
16 GND
17 RXE3-
18 RXE3+
19 GND
20 BLON OUT
Description
+12.0V power supply
+12.0V power supply
Ground
Ground
Negative LVDS differential data input. Channel E0 (even)
Positive LVDS differential data input. Channel E0 (even)
Ground
Negative LVDS differential data input. Channel E1 (even)
Positive LVDS differential data input. Channel E1 (even)
Ground
Negative LVDS differential data input. Channel E2 (even)
Positive LVDS differential data input. Channel E2 (even)
Ground
Negative LVDS differential clock input. (even)
Positive LVDS differential clock input. (even)
Ground
Negative LVDS differential data input. Channel E3 (even)
Positive LVDS differential data input. Channel E3 (even)
Ground
Back-Light ON signal. 3.3V CMOS Output.
This signal turns high at 50-80 ms after VCC applied.
J2(Slave) : Left side(Front View)
Signal Description (J2)
Pin Name
1 VCC
2 VCC
3 GND
4 GND
5 RXO0-
6 RXO0+
7 GND
8 RXO1-
9 RXO1+
10 GND
11 RXO2-
12 RXO2+
13 GND
14 RXOC-
15 RXOC+
16 GND
17 RXO3-
18 RXO3+
19 GND
20 SELLVDS
Description
+12.0V power supply
+12.0V power supply
Ground
Ground
Negative LVDS differential data input. Channel O0 (odd)
Positive LVDS differential data input. Channel O0 (odd)
Ground
Negative LVDS differential data input. Channel O1 (odd)
Positive LVDS differential data input. Channel O1 (odd)
Ground
Negative LVDS differential data input. Channel O2 (odd)
Positive LVDS differential data input. Channel O2 (odd)
Ground
Negative LVDS differential clock input. (odd)
Positive LVDS differential clock input. (odd)
Ground
Negative LVDS differential data input. Channel O3 (odd)
Positive LVDS differential data input. Channel O3 (odd)
Ground
Tie to GND:VESA Mode; Tie to 3.3V :JEITA Mode
Version 2.1
18 January, 2011
The copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited.
12 / 30
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12 Page





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