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R5F10EBEANA Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer R5F10EBEANA
Beschreibung Combines Multi-channel 12-Bit A/D Converter
Hersteller Renesas Technology
Logo Renesas Technology Logo 




Gesamt 30 Seiten
R5F10EBEANA Datasheet, Funktion
Preliminary Datasheet
Specifications in this document are tentative and subject to change.
RL78/G1A
R01DS0151EJ0001
RENESAS MCU
Rev.0.01
2011.12.26
Combines Multi-channel 12-Bit A/D Converter, True Low Power Platform (as low as 66 µA/MHz, and
0.57 µA for RTC + LVD), 1.6 V to 3.6 V operation, 16 to 64 Kbyte Flash, 41 DMIPS at 32 MHz
1. OUTLINE
1.1 Features
Ultra-Low Power Technology
1.6 V to 3.6 V operation from a single supply
Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31
µA
Halt (RTC + LVD): 0.57 µA
Snooze: T.B.D.
Operating: 66 µA/MHz
16-bit RL78 CPU Core
Delivers 41 DMIPS at maximum operating frequency
of 32 MHz
Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
CISC Architecture (Harvard) with 3-stage pipeline
Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
MAC: 16 x 16 to 32-bit result in 2 clock cycles
16-bit barrel shifter for shift & rotate in 1 clock cycle
1-wire on-chip debug function
Code Flash Memory
Density: 16 KB to 64 KB
Block size: 1 KB
On-chip single voltage flash memory with protection
from block erase/writing
Self-programming with secure boot swap function
and flash shield window function
Data Flash Memory
Data Flash with background operation
Data flash size: 4 KB
Erase Cycles: 1 Million (typ.)
Erase/programming voltage: 1.8 V to 3.6 V
RAM
2 KB to 4 KB size options
Supports operands or instructions
Back-up retention in all modes
High-speed On-chip Oscillator
32 MHz with +/1% accuracy over voltage (1.8 V to
3.6 V) and temperature (20 °C to +85 °C)
Pre-configured settings: 32 MHz, 24 MHz, 16 MHz,
12 MHz, 8 MHz, 4 MHz & 1 MHz
Reset and Supply Management
Power-on reset (POR) monitor/generator
Low voltage detection (LVD) with 12 setting options
(Interrupt and/or reset function)
Data Memory Access (DMA) Controller
Up to 2 fully programmable channels
Transfer unit: 8- or 16-bit
Multiple Communication Interfaces
Up to 6 x I2C master
Up to 1 x I2C multi-master
Up to 6 x CSI/SPI (7-, 8-bit)
Up to 3 x UART (7-, 8-, 9-bit)
Up to 1 x LIN
Extended-Function Timers
Multi-function 16-bit timers: Up to 8 channels
Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
Interval Timer: 12-bit, 1 channel
15 kHz watchdog timer: 1 channel (window function)
Rich Analog
ADC: Up to 28 channels, 12-bit resolution, 3.375 µs
conversion time
Supports 1.6 V
Internalwww.DataSheet.net/ voltage reference (1.45 V)
On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
Flash memory CRC calculation
RAM parity error check
RAM write protection
SFR write protection
Illegal memory access detection
Clock stop/ frequency detection
ADC self-test
General Purpose I/O
3.6 V tolerant, high-current (up to 20 mA per pin)
Open-Drain, Internal Pull-up support
Operating Ambient Temperature
Standard: 40 °C to +85 °C
Package Type and Pin Count
From 3 mm x 3 mm to 10 mm x 10 mm
QFP: 48, 64
QFN: 32, 48
LGA: 25
BGA: 64
R01DS0151EJ0001 Rev.0.01
2011.12.26
Page 1 of 76
Datasheet pdf - http://www.DataSheet4U.co.kr/






R5F10EBEANA Datasheet, Funktion
Under development
RL78/G1A
Preliminary document
Specifications in this document are tentative and subject to change.
1.3.3 48-pin products
48-pin plastic LQFP (fine pitch) (7 × 7)
1. OUTLINE
P120/ANI19
P41/ANI30/TI07/TO07
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
36 35 34 33 32 31 30 29 28 27 26 25
37 24
38 23
39 22
40 21
41 20
42 19
43 18
44 17
45 16
46 15
47 14
48 13
1 2 3 4 5 6 7 8 9 10 11 12
www.DataSheet.net/
AVSS
AVDD
P150/ANI8
P10/ANI18/SCK00/SCL00/(KR0)
P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)
P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)
P13/ANI22/SO20/TxD2/(KR3)
P14/ANI23/SI20/SDA20/RxD2/(KR4)
P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5)
P16/TI01/TO01/INTP5
P51/ANI25/SO11/INTP2
P50/ANI26/SI11/SDA11/INTP1
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0151EJ0001 Rev.0.01
2011.12.26
Page 6 of 76
Datasheet pdf - http://www.DataSheet4U.co.kr/

6 Page









R5F10EBEANA pdf, datenblatt
Under development
RL78/G1A
Preliminary document
Specifications in this document are tentative and subject to change.
1.5.2 32-pin products
TI00/P02
TO00/P03
TI03/TO03/P31
RxD2/P14
RxD0/P11
TxD0/P12
RxD1/P03
TxD1/P02
SCK00/P10
SI00/P11
SO00/P12
SCK11/P30
SI11/P50
SO11/P51
SCL00/P10
SDA00/P11
SCL11/P30
SDA11/P50
TIMER ARRAY
UNIT (8ch)
ch0
ch1
ch2
ch3
ch4
ch5
ch6
ch7
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
REAL-TIME
CLOCK
SERIAL ARRAY
UNIT0 (4ch)
UART0
UART1
CSI00
CSI11
IIC00
IIC11
RxD2/P14
TxD2/P13
SCK20/P15
SI20/P14
SO20/P13
SCL20/P15
SDA20/P14
SERIAL ARRAY
UNIT1 (2ch)
UART2
LINSEL
CSI20
IIC20
INTERVAL
TIMER
RL78
CPU
CORE
CODE FLASH MEMORY
DATA FLASH MEMORY
RAM
VDD
VSS
TOOLRxD/P11,www.DataSheet.net/
TOOLTxD/P12
SERIAL
INTERFACE IICA0
SDAA0/P61
SCLA0/P60
BUZZER OUTPUT
2
PCLBUZ0/P31,
PCLBUZ1/P15
CLOCK OUTPUT
CONTROL
MULTIPLIER&
DIVIDER,
MULITIPLY-
ACCUMULATOR
DIRECT MEMORY
ACCESS CONTROL
BCD
ADJUSTMENT
1. OUTLINE
PORT 0
2 P02, P03
PORT 1
6 P10 to P15
PORT 2
5 P20 to P24
PORT 3
2 P30, P31
PORT 4
P40
PORT 5
2 P50, P51
PORT 6
3 P60 to P62
PORT 7
P70
PORT 12
P120
2 P121, P122
PORT 13
KEY RETURN
A/D CONVERTER
P137
KR0/P70
(KR0/P10 to KR5/P15)
1(6) (KR0/P120, KR1/P02, KR2/P03,
KR3/P22 to KR5/P24)
5
ANI0/P20 to
ANI4/P24
ANI16/P03, ANI17/P02, ANI18/P10,
13 ANI19/P120 to ANI24/P15, ANI26/P50,
ANI27/P30, ANI28/P70, ANI29/P31
AVREFP/P20
AVREFM/P21
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
ON-CHIP DEBUG
TOOL0/P40
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
RESET
X1/P121
X2/EXCLK/P122
VOLTAGE
REGULATOR
INTERRUPT
CONTROL
REGC
RxD2/P14
INTP0/P137
INTP1/P50,
2 INTP2/P51
2
INTP3/P30,
INTP4/P31
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR).
R01DS0151EJ0001 Rev.0.01
2011.12.26
Page 12 of 76
Datasheet pdf - http://www.DataSheet4U.co.kr/

12 Page





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