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PDF RDA5851S Data sheet ( Hoja de datos )
| Número de pieza | RDA5851S | |
| Descripción | Bluetooth Multi-Media Single-Chip Terminal | |
| Fabricantes | RDA | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de RDA5851S (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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RDA5851S Datasheet V1.01
RDA5851S Bluetooth Multi-Media Single-Chip Terminal
FEATURES
● External Memory Interface
Integrated 8Mbit(or 1MByte) Flash on chip
Power efficient using retention technology to
avoid floating lines
Flexible IO voltage
● Power Management
Power On reset control
Internal 32K OSC for standby/ shutoff/ sleep
state
Battery charger (from USB or AC charger)
Integrated all internal voltages from VBAT
Provide all LDOs for external components
● User Interface
ADC serial interface Keypad
● Connectivity
USB 1.1 Device
UART interface
1 SD controller
I2C controller
I2S controller
General Purpose I/Os
1 GPADC, 10bits, 1 channel
● Audio
1 channel voice ADC, 8kHz, 13 bits/sample
for microphone
Voice DAC, 8kHz, 13 bits/sample for
receiver
High fidelity Stereo DAC, up to 48kHz, 16
bits per sample
Stereo analog audio line input
● Debug
Host debug interface allowing non intrusive
in depth investigation
GDB debugger
Execution logger and profiling through debug
port
High level text based debugging using Host
debug or USB
● FM
Integrated Broadcast FM tuner which can be
tuned world-wide frequency band
● Bluetooth
Integrated Bluetooth SoC complaint with 2.1
+ EDR standard
APPLICATIONS
The high level of integration achieved on RDA5851S
allows for highly integrated bluetooth music box and
stereo headset without increasing the BOM.
RDA Microelectronics Inc. CONFIDENTIAL
1 / 72
1 page  
RDA5851S Datasheet V1.01
Figure Index
Figure B.1: XCPU Block Diagram .............................................................................................................. 11
Figure B.2: Typical transfer operation ........................................................................................................ 22
Figure B.3: Debug channel block diagram ................................................................................................. 24
Figure B.4: General Message Format ........................................................................................................ 28
Figure B.5: Read Return Message Format ................................................................................................ 28
Figure B.6: Event Message Format ........................................................................................................... 28
Figure B.7: Tx Switch STM ........................................................................................................................ 30
Figure B.8: IrDA SIR Data Format ............................................................................................................. 30
Figure B.9: YUV 4:2:2 Subsampling ........................................................................................................... 42
Figure B.10: SPI Write & Read Timing ....................................................................................................... 46
Figure B.11: PMU Power ON ..................................................................................................................... 47
Figure B.12: POR triggered by POWKEY press ........................................................................................ 48
Figure B.13: Principle schematic for Power-Profiles usage ........................................................................49
Figure B.14: Charging I-V Curve ................................................................................................................ 51
Figure B.15: PLL Clock Path ...................................................................................................................... 52
Figure B.16: USB PHY FS 1.1 .................................................................................................................. 53
Figure B.17: GPADC Timing Diagram ....................................................................................................... 54
Figure B.18: FM Tuner Block Diagram ....................................................................................................... 55
Figure B.19: Bluetooth Block Diagram ....................................................................................................... 57
Figure E.1: SCLK Timing Diagram ............................................................................................................. 83
Figure E.2: SPI Write Timing Diagram ...................................................................................................... 83
Figure E.3: SPI Read Timing Diagram ....................................................................................................... 84
Figure G.1: RDA5851 Ball out diagram ..................................................................................................... 86
RDA Microelectronics Inc. CONFIDENTIAL
5 / 72
5 Page 
RDA5851S Datasheet V1.01
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Figure B.1: XCPU Block Diagram
32-bit Instruction Set
Instruction Formats
The RISC processor supports three instruction formats:
R – Register base instruction format
● RD –Target register
● RS – First operand
● RT – Second operand
● SHAMT – Shift amount for shift instructions
● S Code – Instruction code for R type Instructions
0 RS RT RD SHAMT
I – Immediate operand instruction format
● Opcode –Instruction Code
● RS – Source or Base register
● RT – Target Register or Reg-Immediate
RDA Microelectronics Inc. CONFIDENTIAL
S Code
11 / 72
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