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GTLP18T612MEA Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer GTLP18T612MEA
Beschreibung 18-Bit LVTTL/GTLP Universal Bus Transceiver
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 9 Seiten
GTLP18T612MEA Datasheet, Funktion
May 1999
Revised September 1999
GTLP18T612
18-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP18T612 is an 18-bit universal bus transceiver
which provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface for
cards operating at LVTTL logic levels and a backplane
operating at GTLP logic levels. High speed backplane
operation is a direct result of GTLP’s reduced output swing
(< 1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
less than 0.5V, the output HIGH is 1.5V and the receiver
threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic
levels
s Edge Rate Control to minimize noise on the GTLP port
s Power up/down high impedance for live insertion
s External VREF pin for receiver threshold
s BiCMOS technology for low power dissipation
s Bushold data inputs on A Port eliminates the need for
external pull-up resistors for unused inputs
s LVTTL compatible Driver and Control inputs
s Flow-through architecture optimizes PCB layout
s Open drain on GTLP to support wired-or connection
s A-Port source/sink 24 mA/+24 mA
s B-Port sink capability +50 mA
s D-type flip-flop, latch and transparent data paths
Ordering Code:
Order Number Package Number
Package Description
GTLP18T612MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
GTLP18T612MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation DS500169
www.fairchildsemi.com






GTLP18T612MEA Datasheet, Funktion
AC Electrical Characteristics
Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted).
CL = 30 pF for B Port and CL = 50 pF for A Port.
Symbol
From
(Input)
To
(Output)
Typ
Min
(Note 11)
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
A
LEAB
CLKAB
B 2.1 4.1
1.0 2.7
B 2.2 4.2
1.0 2.4
B 2.2 4.4
1.0 2.5
tPLH
tPHL
tRISE
tFALL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
OEAB
B
Transition time, B outputs (20% to 80%)
Transition time, B outputs (20% to 80%)
BA
LEBA
A
CLKBA
A
2.0 3.8
1.0 2.6
3.1
2.1
1.8 3.8
1.8 3.8
0.3 2.2
0.4 2.4
0.5 2.4
0.6 2.6
tPZH, tPZL
tPHZ, tPLZ
OEBA
A 0.3 2.7
0.3 2.5
Note 11: All typical values are at VCC = 3.3V, and TA = 25°C.
Max
6.3
4.4
6.3
4.2
6.5
4.4
5.6
4.3
5.8
5.8
4.6
4.6
4.6
4.6
5.2
5.2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Extended Electrical Characteristics
Over recommended ranges of supply voltage and operating free-air temperature VREF = 1.0V (unless otherwise noted).
CL = 30 pF for B Port and CL = 50 pF for A Port.
Symbol
From
(Input)
To
(Output)
Min
Typ
(Note 11)
Max
Unit
tOSLH (Note 12)
AB
0.8 1.0 ns
tOSHL (Note 12)
0.3 0.5 ns
tPV(HL) (Note 13)(Note 14)
A
B
0.8 ns
tOSLH (Note 12)
CLKAB
B
0.9 1.0 ns
tOSHL (Note 12)
0.3 0.5 ns
tPV(HL) (Note 13)(Note 14)
CLKAB
B
0.8 ns
tOSLH (Note 12)
BA
0.7 1.0 ns
tOSHL (Note 12)
0.6 1.0 ns
tOST (Note 12)
BA
0.7 1.1 ns
tPV (Note 13)
BA
1.5 ns
tOSLH (Note 12)
CLKAB
A
0.5 1.0 ns
tOSHL (Note 12)
0.6 1.0 ns
tOST (Note 12)
CLKAB
A
1.1 1.2 ns
tPV (Note 13)
CLKAB
A
1.5 ns
Note 12: tOSHL/tOSLH and tOST - Output to output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs
within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same
direction either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and
statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the
device.
Note 13: tPV - Part to part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device to device.
The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual
skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
Note 14: Due to the open drain structure on GTLP outputs tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the
VTT and RT values on the backplane.
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