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PDF DM74S163 Data sheet ( Hoja de datos )
| Número de pieza | DM74S163 | |
| Descripción | Synchronous 4-Bit Binary Counters | |
| Fabricantes | Fairchild Semiconductor | |
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August 1986
Revised April 2000
DM74S161 • DM74S163
Synchronous 4-Bit Binary Counters
General Description
These synchronous, presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs. They are 4-bit binary counters. The carry output is
decoded by means of a NOR gate, thus preventing spikes
during the normal counting mode of operation. Synchro-
nous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with
each other when so instructed by the count enable inputs
and internal gating. This mode of operation eliminates the
output counting spikes which are normally associated with
asynchronous (ripple clock) counters. A buffered clock
input triggers the four flip-flops on the rising (positive-
going) edge of the clock input waveform.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a LOW level at the load input disables the
counter and causes the outputs to agree with the setup
data after the next clock pulse regardless of the levels of
the enable input.
The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without addi-
tional gating. Instrumental in accomplishing this function
are two count-enable inputs and a ripple carry output. Both
count-enable inputs (P and T) must be HIGH to count, and
input T is fed forward to enable the ripple carry output. The
ripple carry output thus enabled will produce a HIGH-level
output pulse with a duration approximately equal to the
HIGH-level portion of the QA output. This HIGH-level over-
flow ripple carry pulse can be used to enable successive
cascaded stages.
Features
s Synchronously programmable
s Internal look-ahead for fast counting
s Carry output for n-bit cascading
s Synchronous counting
s Load control line
s Diode-clamped inputs
Ordering Code:
Order Number
DM74S161N
DM74S163N
Package Number
Package Description
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS006471
www.fairchildsemi.com
1 page  
Absolute Maximum Ratings(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
5.5V
0°C to +70°C
−65°C to +150°C
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
Parameter
VCC Supply Voltage
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
IOH HIGH Level Output Current
IOL LOW Level Output Current
fCLK Clock Frequency (Note 2)
Clock Frequency (Note 3)
tW
Pulse Width (Note 2)
Clock
Clear (Note 5)
Pulse Width (Note 3)
Clock
Clear (Note 5)
tSU
Setup Time (Note 2)
Data
Enable P or T
Load
Clear (Note 4)
Setup Time (Note 3)
Data
Enable P or T
Load
Clear (Note 4)
tH
Hold Time (Note 2)
Data
Others
Hold Time (Note 3)
Data
Others
tREL Load or Clear Release Time (Note 2)
Load or Clear Release Time (Note 3)
TA Free Air Operating Temperature
Note 2: CL = 15 pF, RL = 280Ω, TA = 25°C and VCC = 5V.
Note 3: CL = 50 pF, RL = 280Ω, TA = 25°C and VCC = 5V.
Note 4: Applies only to the DM74S163 which has synchronous clear inputs.
Note 5: Applies only to the DM74S161 which has asynchronous clear inputs.
Min
4.75
2
0
0
10
10
12
12
4
12
14
14
5
14
16
16
3
0
5
2
12
14
0
Nom
5
Max
5.25
0.8
−1
20
40
35
70
Units
V
V
V
mA
mA
MHz
ns
ns
ns
ns
°C
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet DM74S163.PDF ] | |
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