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GT28F160S3-120 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer GT28F160S3-120
Beschreibung WORD-WIDE FlashFile MEMORY FAMILY
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
GT28F160S3-120 Datasheet, Funktion
E
ADVANCE INFORMATION
WORD-WIDE
FlashFile™ MEMORY FAMILY
28F160S3, 28F320S3
Includes Extended Temperature Specifications
n Two 32-Byte Write Buffers
2.7 µs per Byte Effective
Programming Time
n Low Voltage Operation
2.7V or 3.3V VCC
2.7V, 3.3V or 5V VPP
n 100 ns Read Access Time (16 Mbit)
110 ns Read Access Time (32 Mbit)
n High-Density Symmetrically-Blocked
Architecture
32 64-Kbyte Erase Blocks (16 Mbit)
64 64-Kbyte Erase Blocks (32 Mbit)
n System Performance Enhancements
STS Status Output
n Industry-Standard Packaging
µBGA* package, SSOP, and
TSOP (16 Mbit)
µBGA* package and SSOP (32 Mbit)
n Cross-Compatible Command Support
Intel Standard Command Set
Common Flash Interface (CFI)
Scaleable Command Set (SCS)
n 100,000 Block Erase Cycles
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Erase/Program Lockout
during Power Transitions
n Configurable x8 or x16 I/O
n Automation Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n ETOX™ V Nonvolatile Flash
Technology
Intel’s Word-Wide FlashFile™ memory family provides high-density, low-cost, non-volatile, read/write storage
solutions for a wide range of applications. The Word-Wide FlashFile memories are available at various
densities in the same package type. Their symmetrically-blocked architecture, flexible voltage, and extended
cycling provide highly flexible components suitable for resident flash arrays, SIMMs, and memory cards.
Enhanced suspend capabilities provide an ideal solution for code or data storage applications. For secure
code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the Word-Wide FlashFile memories offer three levels of protection: absolute protection
with VPP at GND, selective block locking, and program/erase lockout during power transitions. These
alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. It comes in the
industry-standard 56-lead SSOP and µBGA packages. In addition, the 16-Mb device is available in the
industry-standard 56-lead TSOP package.
June 1997
Order Number: 290608-001






GT28F160S3-120 Datasheet, Funktion
28F160S3, 28F320S3
E
The device incorporates two Write Buffers of 32
bytes (16 words) to allow optimum-performance
data programming. This feature can improve
system program performance by up to four times
over non-buffer programming.
Individual block locking uses a combination of block
lock-bits to lock and unlock blocks. Block lock-bits
gate block erase, full chip erase, program and write
to buffer operations. Lock-bit configuration
operations (Set Block Lock-Bit and Clear Block
Lock-Bits commands) set and clear lock-bits.
The Status Register and the STS pin in RY/BY#
mode indicate whether or not the device is busy
executing an operation or ready for a new
command. Polling the Status Register, system
software retrieves WSM feedback. STS in RY/BY#
mode gives an additional indicator of WSM activity
by providing a hardware status signal. Like the
Status Register, RY/BY#-low indicates that the
WSM is performing a block erase, program, or lock-
bit operation. RY/BY#-high indicates that the WSM
is ready for a new command, block erase is
suspended (and program is inactive), program is
suspended, or the device is in deep power-down
mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
The BYTE# pin allows either x8 or x16 read/writes
to the device. BYTE# at logic low selects 8-bit
mode with address A0 selecting between the low
byte and high byte. BYTE# at logic high enables
16-bit operation with address A1 becoming the
lowest order address. Address A0 is not used in 16-
bit mode.
When one of the CEX# pins (CE0#, CE1#) and RP#
pins are at VCC, the component enters a CMOS
standby mode. Driving RP# to GND enables a deep
power-down mode which significantly reduces
power consumption, provides write protection,
resets the device, and clears the Status Register. A
reset time (tPHQV) is required from RP# switching
high until outputs are valid. Likewise, the device
has a wake time (tPHEL) from RP#-high until writes
to the CUI are recognized.
1.3 Pinout and Pin Description
The 16-Mbit device is available in the 56-lead
TSOP, 56-lead SSOP and µBGA packages. The
32- Mb device is available in the 56-lead SSOP and
µBGA packages. The pinouts are shown in Figures
2, 3 and 4.
DQ0 - DQ15
16-Mbit: A0- A20
32-Mbit: A0 - A21
Input Buffer
Address
Latch
Address
Counter
Y-Decoder
X-Decoder
Output Buffer
Input Buffer
Query
Identifier
Register
Status
Register
Data
Comparator
Y-Gating
Multiplexer
16-Mbit: Thirty-two
32-Mbit: Sixty-four
64-Kbyte Blocks
Command
User
Interface
I/O Logic
VCC
BYTE#
CE#
WE#
OE#
RP#
WP#
Write State
Machine
Program/Erase
Voltage Switch
STS
VPP
VCC
GND
Figure 1. Block Diagram
6 ADVANCE INFORMATION

6 Page









GT28F160S3-120 pdf, datenblatt
28F160S3, 28F320S3
3.0 BUS OPERATION
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
3.1 Read
Block information, query information, identifier
codes and Status Registers can be read
independent of the VPP voltage.
The first task is to place the device into the
desired read mode by writing the appropriate
read-mode command (Read Array, Query, Read
Identifier Codes, or Read Status Register) to the
CUI. Upon initial device power-up or after exit
from deep power-down mode, the device
automatically resets to read array mode. Control
pins dictate the data flow in and out of the
component. CE0#, CE1# and OE# must be driven
active to obtain data at the outputs. CE0# and
CE1# are the device selection controls, and,
when both are active, enable the selected
memory device. OE# is the data output (DQ0
DQ15) control: When active it drives the selected
memory data onto the I/O bus. WE# must be at
VIH and RP# must be at VIH. Figure 17 illustrates
a read cycle.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0–DQ15 are
placed in a high-impedance state.
3.3 Standby
CE0# or CE1# at a logic-high level (VIH) places
the device in standby mode, substantially
reducing device power consumption. DQ0–DQ15
(or DQ0– DQ7 in x8 mode) outputs are placed in
a high-impedance state independent of OE#. If
deselected during block erase, programming, or
lock-bit configuration, the device continues
functioning and consuming active power until the
operation completes.
E
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read mode, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off all internal circuits. RP# must be
held low for time tPLPH. Time tPHQV is required
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI
resets to read array mode, and the Status
Register is set to 80H.
During block erase, programming, or lock-bit
configuration modes, RP#-low will abort the
operation. STS in RY/BY# mode remains low
until the reset operation is complete. Memory
contents being altered are no longer valid; the
data may be partially corrupted after
programming or partially altered after an erase or
lock-bit configuration. Time tPHWL is required after
RP# goes to logic-high (VIH) before another
command can be written.
It is important in any automated system to assert
RP# during system reset. When the system
comes out of reset, it expects to read from the
flash memory. Automated flash memories
provide status information when accessed during
block erase, programming, or lock-bit
configuration modes. If a CPU reset occurs with
no flash memory reset, proper CPU initialization
may not occur because the flash memory may be
providing status information instead of array data.
Intel’s Flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that
resets the system CPU.
3.5 Read Query Operation
The read query operation outputs block status,
Common Flash Interface (CFI) ID string, system
interface, device geometry, and Intel-specific
extended query information.
12 ADVANCE INFORMATION

12 Page





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