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GT28F016C3B90 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer GT28F016C3B90
Beschreibung 3 VOLT ADVANCED+ BOOT BLOCK 8-/ 16-/ 32-MBIT FLASH MEMORY FAMILY
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
GT28F016C3B90 Datasheet, Funktion
E
PRODUCT PREVIEW
3 VOLT ADVANCED+ BOOT BLOCK
8-, 16-, 32-MBIT
FLASH MEMORY FAMILY
28F008C3, 28F016C3, 28F032C3
28F800C3, 28F160C3, 28F320C3
n Flexible SmartVoltage Technology
2.7 V–3.6 V Read/Program/Erase
2.7 V or 1.65 V I/O Option Reduces
Overall System Power
12 V for Fast Production
Programming
n High Performance
2.7 V–3.6 V: 90 ns Max Access Time
3.0 V–3.6 V: 80 ns Max Access Time
n Optimized Architecture for Code Plus
Data Storage
Eight 8-Kbyte Blocks,
Top or Bottom Locations
Up to Sixty-Three 64-KB Blocks
Fast Program Suspend Capability
Fast Erase Suspend Capability
n Flexible Block Locking
Lock/Unlock Any Block
Full Protection on Power-Up
WP# Pin for Hardware Block
Protection
VPP = GND Option
VCC Lockout Voltage
n Low Power Consumption
9 mA Typical Read Power
10 µA Typical Standby Power with
Automatic Power Savings Feature
n Extended Temperature Operation
–40 °C to +85 °C
n Easy-12 V
Faster Production Programming
No Additional System Logic
n 128-bit Protection Register
64-bit Unique Device Identifier
64-bit User Programmable OTP
Cells
n Extended Cycling Capability
Minimum 100,000 Block Erase
Cycles
n Flash Data Integrator Software
Flash Memory Manager
System Interrupt Manager
Supports Parameter Storage,
Streaming Data (e.g., voice)
n Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
n SRAM-Compatible Write Interface
n Cross-Compatible Command Support
Intel Basic Command Set
Common Flash Interface
n x 16 for High Performance
48-Ball µBGA* Package
48-Lead TSOP Package
n x 8 I/O for Space Savings
48-Ball µBGA* Package
40-Lead TSOP Package
n 0.25 µ ETOX™ VI Flash Technology
The 0.25 µm 3 Volt Advanced+ Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a
feature-rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage
capability (2.7 V read, program and erase) with high-speed, low-power operation. Flexible block locking
allows any block to be independently locked or unlocked. Add to this the Intel-developed Flash Data
Integrator (FDI) software and you have a cost-effective, flexible, monolithic code plus data storage solution on
the market today. 3 Volt Advanced+ Boot Block products will be available in 48-lead TSOP, 40-lead TSOP,
and 48-ball µBGA* packages. Additional information on this product family can be obtained by accessing
Intel’s WWW page: http://www.intel.com/design/flcomp.
May 1998
Order Number: 290645-001






GT28F016C3B90 Datasheet, Funktion
3 VOLT ADVANCED+ BOOT BLOCK
E
1.2 Product Overview
Intel provides secure low voltage memory solutions
with the Advanced Boot Block family of products. A
new block locking feature allows instant
locking/unlocking of any block with zero-latency. A
128-bit protection register allows unique flash
device identification.
Discrete supply pins provide single voltage read,
program, and erase capability at 2.7 V while also
allowing 12 V VPP for faster production
programming. Easy-12 V, a new feature designed
to reduce external logic, simplifies board designs
when combining 12 V production programming with
2.7 V in-field programming.
The 3 Volt Advanced+ Boot Block flash memory
products are available in either x8 or x16 packages
in the following densities: (see Section 6, Ordering
Information)
8-Mbit (8,388,608 bit) flash memories organized
as either 512 Kwords of 16 bits each or 1024
Kbytes or 8 bits each.
16-Mbit (16,777,216 bit) flash memories
organized as either 1024 Kwords of 16 bits
each or 2048 Kbytes of 8 bits each.
32-Mbit (33,554,432 bit) flash memories
organized as either 2048 Kwords of 16 bits
each or 4096 Kbytes of 8 bits each.
Eight 8-KB parameter blocks are located at either
the top (denoted by -T suffix) or the bottom (-B
suffix) of the address map in order to accommodate
different microprocessor protocols for kernel code
location. The remaining memory is grouped into 64-
Kbyte main blocks.
All blocks can be locked or unlocked instantly to
provide complete protection for code or data. (see
Section 3.3 for details).
The Command User Interface (CUI) serves as the
interface between the microprocessor or
microcontroller and the internal operation of the
flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and
timings necessary for program and erase
operations, including verification, thereby
unburdening the microprocessor or microcontroller.
The status register indicates the status of the WSM
by signifying block erase or word program
completion and status.
Program and erase automation allows program and
erase operations to be executed using an industry-
standard two-write command sequence to the CUI.
Program operations are performed in word or byte
increments. Erase operations erase all locations
within a block simultaneously. Both program and
erase operations can be suspended by the system
software in order to read from any other block. In
addition, data can be programmed to another block
during an erase suspend.
The 3 Volt Advanced+ Boot Block flash memories
offer two low power savings features: Automatic
Power Savings (APS) and standby mode. The
device automatically enters APS mode following the
completion of a read cycle. Standby mode is
initiated when the system deselects the device by
driving CE# inactive. Combined, these two power
savings features significantly reduce power
consumption.
The device can be reset by lowering RP# to GND.
This provides CPU-memory reset synchronization
and additional protection against bus noise that
may occur during system reset and power-up/down
sequences (see Section 3.5 and 3.6).
Refer to the DC Characteristics Section 4.4 for
complete current and voltage specifications. Refer
to the AC Characteristics Sections 4.5 and 4.6, for
read and write performance specifications. Program
and erase times and shown in Section 4.7.
2.0 PRODUCT DESCRIPTION
This section provides device pin descriptions and
package pinouts for the 3 Volt Advanced+ Boot
Block flash memory family, which is available in 40-
Lead TSOP (x8, Figure 1), 48-lead TSOP (x16,
Figure 2) and 48-ball µBGA packages (Figures 3
and 4).
2.1 Package Pinouts
In each diagram, upgrade pins from one density to
the next are circled.
6 PRODUCT PREVIEW

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GT28F016C3B90 pdf, datenblatt
3 VOLT ADVANCED+ BOOT BLOCK
E
3.1.4
RESET
From read mode, RP# at VIL for time tPLPH
deselects the memory, places output drivers in a
high-impedance state, and turns off all internal
circuits. After return from reset, a time tPHQV is
required until the initial read access outputs are
valid. A delay (tPHWL or tPHEL) is required after
return from reset before a write can be initiated.
After this wake-up interval, normal operation is
restored. The CUI resets to read array mode, and
the status register is set to 80H. This case is shown
in Figure 11A.
If RP# is taken low for time tPLPH during a program
or erase operation, the operation will be aborted
and the memory contents at the aborted location
(for a program) or block (for an erase) are no longer
valid, since the data may be partially erased or
written. The abort process goes through the
following sequence: When RP# goes low, the
device shuts down the operation in progress, a
process which takes time tPLRH to complete. After
this time tPLRH, the part will either reset to read
array mode (if RP# has gone high during tPLRH,
Figure 11B) or enter reset mode (if RP# is still logic
low after tPLRH, Figure 11C). In both cases, after
returning from an aborted operation, the relevant
time tPHQV or tPHWL/tPHEL must be waited before a
read or write operation is initiated, as discussed in
the previous paragraph. However, in this case,
these delays are referenced to the end of tPLRH
rather than when RP# goes high.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, processor expects to read from
the flash memory. Automated flash memories
provide status information when read during
program or block erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel’s flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
3.1.5
WRITE
A write takes place when both CE# and WE# are
low and OE# is high. Commands are written to the
Command User Interface (CUI) using standard
microprocessor write timings to control flash
operations. The CUI does not occupy an
12
addressable memory location. The address and
data buses are latched on the rising edge of the
second WE# or CE# pulse, whichever occurs first.
Figure 10 illustrates a program and erase operation.
The available commands are shown in Table 6, and
Appendix A provides detailed information on
moving between the different modes of operation
using CUI commands.
There are two commands that modify array data:
Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User
Interface (CUI) initiates a sequence of internally-
timed functions that culminate in the completion of
the requested task (unless that operation is aborted
by either RP# being driven to VIL for tPLRH or an
appropriate suspend command).
3.2 Modes of Operation
The flash memory has four read modes and two
write modes. The read modes are read array, read
configuration, read status, and read query. The
write modes are program and block erase. Three
additional modes (erase suspend to program, erase
suspend to read and program suspend to read) are
available only during suspended operations. These
modes are reached using the commands
summarized in Tables 5 and 6. A comprehensive
chart showing the state transitions is in Appendix A.
3.2.1
READ ARRAY
When RP# transitions from VIL (reset) to VIH, the
device defaults to read array mode and will respond
to the read control inputs (CE#, address inputs, and
OE#) without any additional CUI commands.
When the device is in read array mode, four control
signals control data output:
WE# must be logic high (VIH)
CE# must be logic low (VIL)
OE# must be logic low (VIL)
RP# must be logic high (VIH)
In addition, the address of the desired location must
be applied to the address pins. If the device is not
in read array mode, as would be the case after a
program or erase operation, the Read Array
command (FFH) must be written to the CUI before
array reads can take place.
PRODUCT PREVIEW

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