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GS9015ACPJ Schematic ( PDF Datasheet ) - ETC

Teilenummer GS9015ACPJ
Beschreibung Serial Digital Reclocker
Hersteller ETC
Logo ETC Logo 




Gesamt 13 Seiten
GS9015ACPJ Datasheet, Funktion
GENLINXGS9015A
Serial Digital Reclocker
DATA SHEET
FEATURES
• reclocking of SMPTE 259M signals
• operational to 400 Mb/s
• adjustment free reclocker when used with the
GS9000B or GS9000S decoder and GS9010A
Automatic Tuning Sub-system
• 28 pin PLCC packaging
APPLICATIONS
• 4ƒSC, 4:2:2 and 360 Mb/s serial digital interfaces
ORDERING INFORMATION
PART NUMBER
GS9015ACPJ
GS9015ACTJ
PACKAGE
28 Pin PLCC
28 Pin PLCC Tape
TEMPERATURE
0O C to 70O C
0O C to 70O C
DEVICE DESCRIPTION
The GS9015A is a monolithic IC designed to receive SMPTE
259M serial digital video signals. This device performs the
function of data and clock recovery. It interfaces directly with
the GENLINXGS9000B or GS9000S Decoder.
While there are no plans to discontinue the GS9015A, Gennum
has developed a successor product with improved features
and performance called the GS9035. The GS9035 is
recommended for new designs.
The VCO centre frequencies are controlled by external resistors
which can be selected by applying a two bit binary code to the
Standards Select input pins. Alternatively, the GS9015A can
be used with the GS9010A to form an adjustment free reclocker
system.
The GS9015A is packaged in a 28 pin PLCC operating from
a single +5 or -5 volt supply.
SPECIAL NOTE: R and R are functional over a
VCO1
VCO2
reduced temperature range of TA=0°C to 50°C. RVCO0
and RVCO3 are functional over the full temperature range
of TA=0°C to 70°C. This limitation does not affect
operation with the GS9010A ATS.
DIGITAL 5,6
IN
DATA
LATCH
CARRIER 19
DETECT
CARRIER
DETECT
LOOP
FILTER 12
PLL
PHASE
COMPARATOR
÷2
CHARGE
PUMP
VCO
GS9015A
24
25
22
23
SERIAL DATA
SERIAL DATA
SERIAL CLOCK
SERIAL CLOCK
10
ƒ/2
STANDARD
SELECT
20 SS0
21 SS1
13 14 15 17
FUNCTIONAL BLOCK DIAGRAM
Revision Date: April 1998
Document No. 520 - 99 - 05
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946
Web Site: www.gennum.com E-mail: [email protected]






GS9015ACPJ Datasheet, Funktion
INPUT / OUTPUT CIRCUITS cont.
IVCO
(1.9 - 2.4V)
Pin 13 RVCO 0
Pin 14 RVCO 1
Pin 15 RVCO 2
Pin 17 RVCO 3
400
400
400
400
Fig. 4 Pins 13, 14, 15 and 17
VCC
200 200
VCC3
LOOP FILTER
(1.8 - 2.7V)
10k 10k
VCC
VCC
3k
SDO or SCO
Pin 25, 24
SDO or SCO
Pin 23, 22
800
Fig. 5 Pins 25, 24, 23 and 22
520 - 99 - 05
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GS9015ACPJ pdf, datenblatt
Application Note - PCB Layout
Special attention must be paid to component layout when designing high performance serial digital receivers. For background
information on high speed circuit and layout design concepts, refer to Document No. 521-32-00, “Optimizing Circuit and Layout
Design of the GS90005A/15A”. A recommended PCB layout can be found in the Gennum Application Note “EB9010B Deserializer
Evaluation Board”
The use of a star grounding technique is required for the loop filter components of the GS9005A/15A.
Controlled impedance PCB traces should be used for the differential clock and data interconnection between the GS9005A and
the GS9000B or GS9000S. These differential traces must not pass over any ground plane discontinuities. A slot antenna is formed
when a microstrip trace runs across a break in the ground plane.
The series resistors at the parallel data output of the GS9000B or GS9000S are used to slow down the fast rise/fall time of the
GS9000B or GS9000S outputs. These resistors should be placed as close as possible to the GS9000B or GS9000S output pins
to minimize radiation from these pins.
VCC
+5V
DVCC
+5V
SWF
+
10µ
+
10µ
100 3.3k
100
VCC
0.1µ
4 3 2 1 28 27 26
VCC
SERIAL
DIGITAL
INPUT
0.1µ
5
DDI
6
DDI
7 VCC1
8 VEE1
9 VEE1
10 ƒ/2
11 VEE3
GS9015A
25
SDO
SDO 24
SCO 23
SCO 22
SS1 21 VCC
SS0 20
CD 19
5.6p
12 13 14 15 16 17 18 VCC
10n (1)
910
0.1µ
1.2k
GND
DGND
390
390
100
100
100
100
390
390
DGND
100
DGND
DGND
4 3 2 1 28 27 26
5
SDI
6
SDI
7
SCI
8
SCI
9 SS1
10 SS0
11 SST
DVCC
0.1µ
(3)
GS9000B
or GS9000S
25
PD7
24
PD6
23
PD5
22
PD4
PD3 21
PD2 20
PD1 19
100
100
100
100
100
100
100
12 13 14 15 16 17 18
DVCC
100 100
0.1µ
DGND
VCC
DGND
DVCC
0.1µ
1.2k
(2)
50k
68k
22n
STAR
ROUTED
(1) +
6.8µ
6.8µ
+
VCC
120
GS9010A
1
P/N
2
OUT
3
IN-
STDT
VCC
CD
16
15
14
3.3n
4 COMP
5 LF
HSYNC 13
GND 12
6 ƒ/2
OSC 11
7 VCC
8 SWF
DLY 10
FVCAP 9
All resistors in ohms,
0.1µ
all capacitors in microfarads,
all inductors in henries unless otherwise stated.
SWF
VCC
0.1µ
DGND
82n
VCC
180n
VCC
100k
(1)
0.68µ
SYNC WARNING FLAG
HSYNC OUTPUT
PARALLEL DATA BIT 9
PARALLEL DATA BIT 8
PARALLEL DATA BIT 7
PARALLEL DATA BIT 6
PARALLEL DATA BIT 5
PARALLEL DATA BIT 4
PARALLEL DATA BIT 3
PARALLEL DATA BIT 2
PARALLEL DATA BIT 1
PARALLEL DATA BIT 0
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
STANDARD TRUTH TABLE
ƒ/2 P/N
00
01
10
11
STANDARD
4:2:2 - 270
4:2:2 - 360
4ƒsc - NTSC
4ƒsc - PAL
(1) To reduce board space, the two anti-series 6.8 µF capacitors (connected across pins 2 and 3 of
the GS9010A) may be replaced with a 1.0 µF non-polarized capacitor provided that:
(a) the 0.68 µF capacitor connected to the OSC pin (11) of the GS9010A is replaced with a
0.33 µF capacitor and
(b) the GS9005A /15A Loop Filter Capacitor is 10 nF.
(2) Remove this potentiometer if P/N function is not required, and ground pin 16 of the GS9010A.
(3) The GS9000B will operate to a maximum frequency of 370 Mbps. The GS9000S will operate to
a maximum of 300 Mbps.
Fig. 17 Typical Application Circuit
520 - 99 - 05
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