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GS9000CCTJ Schematic ( PDF Datasheet ) - ETC

Teilenummer GS9000CCTJ
Beschreibung Serial Digital Decoder
Hersteller ETC
Logo ETC Logo 




Gesamt 8 Seiten
GS9000CCTJ Datasheet, Funktion
GENLINXGS9000C
Serial Digital Decoder
FEATURES
• fully compatible with SMPTE 259M
• decodes 8 and 10 bit serial digital signals for data
rates to 370Mb/s
• pin and function compatible with GS9000S, GS9000
and GS9000B
• 325mW power dissipation at 270MHz clock rates
• incorporates an automatic standards selection
function with the GS9005A Receiver or GS9015A
Reclocker
• operates from single +5 or -5 volt supply
• enables an adjustment-free Deserializer system
when used with GS9010A and GS9005A or
GS9015A
• 28 pin PLCC packaging
APPLICATIONS
• 4ƒSC, 4:2:2 and 360Mb/s serial digital interfaces
• Automatic standards select controller for serial routing
and distribution applications using GS9005A Receiver or
GS9015A Reclocker
DATA SHEET
DEVICE DESCRIPTION
The GS9000C is a CMOS integrated circuit specifically
designed to deserialize SMPTE 259M serial digital signals
at data rates to 370Mb/s.
The device incorporates a descrambler, serial to parallel
convertor, sync processing unit, sync warning unit and
automatic standards select circuitry.
Differential pseudo-ECL inputs for both serial clock and
data are internally level shifted to CMOS levels. Digital
outputs such as parallel data, parallel clock, HSYNC,
Sync Warning and Standard Select are all TTL compatible.
The GS9000C is designed to directly interface with the
GS9005A Reclocking Receiver to form a complete
SMPTE-serial-in to CMOS level parallel-out deserializer.
The GS9000C may also be used with the GS9010A and
the GS9005A to form an adjustment-free receiving system
which automatically adapts to all serial digital data rates.
The GS9015A can replace the GS9005A in GS9000C
applications where cable equalization is not required.
The GS9000C is packaged in a 28 pin PLCC and operates
from a single 5 volt, ± 5% power supply.
SERIAL DATA IN 5
SERIAL DATA IN 6
LEVEL
SHIFT
SERIAL CLOCK IN 7
8
SERIAL CLOCK IN
LEVEL
SHIFT
SYNC CORRECTION 14
ENABLE
SYNC WARNING 15
CONTROL
STANDARDS SELECT 11
CONTROL
GS9000C
DESCRAMBLER
30 - BIT
SHIFT REG
SP
SCLK
SYNC DETECT
(3FF 000 000 HEX)
Sync
Word
Boundary
PARALLEL
TIMING
GENERATOR
SYNC CORRECTION
Sync Error
SYNC WARNING
(Schmitt Trigger
Comparator)
AUTO STANDARD SELECT
OSC
2 BIT
COUNTER
Hsync Reset
PARALLEL DATA
OUT (10 BITS)
PARALLEL CLOCK
OUT
HSYNC OUTPUT
SYNC WARNING
FLAG
SS0
SS1
FUNCTIONAL BLOCK DIAGRAM
Revision Date: February 2000
Document No. 522 - 49 - 01
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com






GS9000CCTJ Datasheet, Funktion
+5V
3 x 100n
22µ
SDIIN
SDIIN
SCIIN
SCIIN
STANDARDS SELECT BIT 1
STANDARDS SELECT BIT 0
+5V
100k
820p
**
12 13 18
1
VDD VDD VDD HSYNC 17
PD0
DECODER
5 SDI GS9000C
6 SDI
7 SCI
8 SCI
9 SS1
10 SS0
11 SSC
PDI 19
PD2 20
PD3 21
PD4 22
PD5 23
PD6 24
PD7 25
PD8 27
PD9 28
PCLK 16
SCE 14
VSS VSS VSS SWC SWF
2 4 26 15
3
** Locate the three 0.10µF decoupling
capacitors as close as possible to the
corresponding pins on the GS9000C.
Chip capacitors are recommended.
HSYNC OUTPUT
PARALLEL DATA BIT 0
PARALLEL DATA BIT 1
PARALLEL DATA BIT 2
PARALLEL DATA BIT 3
PARALLEL DATA BIT 4
PARALLEL DATA BIT 5
PARALLEL DATA BIT 6
PARALLEL DATA BIT 7
PARALLEL DATA BIT 8
PARALLEL DATA BIT 9
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
10p SYNC WARNING FLAG
13 x 425
39k
+5V
All resistors in ohms,
all capacitors in farads,
unless otherwise specified.
Fig. 8 GS9000C Test Set-Up
With correctly synchronized serial data and clock connected
to the GS9000C, the HSYNC output (pin 1) will toggle for each
HSYNC detected. The Parallel Data bits PD0 through PD9
along with the Parallel Clock can be observed on an
oscilloscope or fed to a logic analyzer. These outputs can
also be fed through a suitable TTL to ECL converter to directly
drive parallel inputs to receiving equipment such as monitors
or digital to analog converters.
In operation, the HSYNC output from the GS9000C decoder
toggles on each occurrence of the timing reference signal
(TRS). The state of the HSYNC output is not significant, just
the time at which it toggles.
SC
DATA
STREAM
HSYNC
OUT
T
R
ACTIVE VIDEO
& H BLANKING
T
R
ACTIVE VIDEO
& H BLANKING
T
R
SSS
4:2:2
DATA
STREAM
EH
S
A BLNK A
VV
ACTIVE
VIDEO
EH
S
A BLNK A
VV
HSYNC
OUT
Fig. 9 Operation of HSYNC Output
The HSYNC output toggles to indicate the presence of the
TRS on the falling edge of PCLK, one data symbol prior to the
output of the first word in the TRS. In the following diagram,
data is indicated in 10 bit Hex.
522 - 49 - 01
PCLK
PDN
XXX 3FF 000 000 XXX
XXX 3FF 000 000 XXX
HSYNC
6
Fig. 10 Operation of HSYNC with Respect to PCLK

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