Datenblatt-pdf.com


CH8438 Schematic ( PDF Datasheet ) - Chrontel

Teilenummer CH8438
Beschreibung Video Multiplexer
Hersteller Chrontel
Logo Chrontel Logo 




Gesamt 11 Seiten
CH8438 Datasheet, Funktion
CHRONTEL
Video Multiplexer with Source Control
CH8438
Preliminary
Features
• Triple 8-bit DAC and buffers support 1280 x 1024
display resolution
• High-speed multiplexing between digital
and analog RGB signals
• 24-bit digital RGB interface supports up to
16.7 million colors
• Supports CCIR601 4:2:2 YCrCb input formats
• Built in YUV-to-RGB color space conversion
• Analog auxiliary inputs with programmable
input attenuation
• 2’s complement input capability on Red and Blue
channels, supporting 4:4:4 YUV format with analog
YUV outputs
• Programmable brightness, contrast, and hue
attributes for the digital input signals
• Programmable switching delay
• Two-wire serial programming
• Enhanced replacement of STV8438
• CMOS technology in 44-pin PQFP
• 5V supply
Description
Chrontel’s CH8438 combines a 24-bit digital video
interface, YUV to RGB converter, three 8-bit DACs, a
high-speed analog multiplexer, an analog input
attenuator, and three video buffers in one integrated
circuit.
The CH8438’s high-speed analog multiplexer allows
simultaneous display of video (digital RGB) with
graphics (analog RGB), making CH8438 ideal for
video games, editing, PC video, and for applications
requiring picture-in-picture capability.
CH8438 provides a 24-bit digital pixel bus interface,
which supports RGB, 4:4:4 YUV and 4:2:2 YCrCb
input formats. With the 4:2:2 YCrCb input format, a
built-in color space converter translates YUV video
information to RGB before muxing with the analog
graphics input, while the 4:4:4 YUV format accepts 2’s
complement Red and Blue data, and provides analog
YUV outputs.
CH8438 has seven 4-bit control registers which are
programmable with the serial interface pins. The
programmable functions include digital input formats;
video attributes of contrast, hue, and brightness; analog
input attenuation; and switching delay.
RAUX
GAUX
BAUX
CLK
DVDD
AVDD
0
ROUT
P[23:0]
24
0
GOUT
0
BOUT
R/C
SD
SC
COM
Rev. 1.0, 8/28/97
SERIAL I/F
12 2 3
3
8-TAP DELAY LINE
DGND
AGND
Figure 1: CH8438 Block Diagram
1






CH8438 Datasheet, Funktion
Preliminary
CH8438
Serial Port Programming
The CH8438 control registers can be downloaded through the two-wire serial port. This is a write only port
with the transfer protocol shown in Figure 10 on page 19. Each data packet consists of a start, a 3-bit address
followed by a “0,” 4 bits of data, and a stop.
The transfer sequence is initiated when a high-to-low transition of serial data (“SD”) occurs while serial clock
(“SC”) is high. Similarly, the transfer sequence is terminated when a low-to-high transition of SD occurs while
SC is high. The transitions of the address and data bits can only occur when SC is in a low state.
SC and SD can be connected to a microcontroller or a video controller’s programmable I/O pins. For more
information, refer to Application Note 18 (AN-18) “Programming the CH8438”.
Control Registers
CH8438 contains seven 4-bit control registers which provide access to basic video attribute control functions.
These registers are accessible via the address bits, A[2:0]. The following sections describe the functions and
the controls available through these registers.
Table 7 • Register Map
Register
R0
Default Value
0H
R1 0H
R2 8H
R3 8H
R4 8H
R5 0H
R6 0H
RTEST
0H
Address
Description
0 0 0 Multiplexer Delay control register
0 0 1 Digital Video Brightness control register
0 1 0 Red or V Digital Input Gain control register
0 1 1 Green or Y Digital Input Gain control register
1 0 0 Blue or U Digital Input Gain control register
1 0 1 Analog Input Attenuation control register
1 1 0 Digital Input Format control register
1 1 1 Reserved
Table 8 • Control Register Summary
Register
R0
Address
A2 A1 A0
000
Register Data
D3 D2 D1 D0
0
MDS2
MDS1
MDS0
R1
0
0
1
PS
DVB2
DVB1
DVB0
R2
0
1
0
RV_G3
RV_G2
RV_G1
RV_G0
R3
0
1
1
GY_G3
GY_G2
GY_G1
GY_G0
R4
1
0
0
BU_G3
BU_G2
BU_G1
BU_G0
R5 1 0 1 0 0 AA1 AA0
R6
1
1
0
COM_INV
DIF2
DIF1
DIF0
RTEST
1
1
1
0
0
0
0
Note: All “0” values of register data D[3:0] shown in table above must be programmed to “0” for proper operation of the
device.
Rev. 1.0, 8/28/97
11

6 Page







SeitenGesamt 11 Seiten
PDF Download[ CH8438 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
CH8438Video MultiplexerChrontel
Chrontel

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche