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R01DS0228EJ0060 Schematic ( Datenblatt PDF ) - Renesas

Teilenummer R01DS0228EJ0060
Beschreibung 450MHz / 600MHz MCU
Hersteller Renesas
Logo Renesas Logo 

Gesamt 30 Seiten
		
R01DS0228EJ0060 Datasheet, Funktion
Preliminary Datasheet
Specifications in this document are tentative and subject to
RZ/T1 Group
R01DS0228EJ0060
Rev.0.60
Nov 14, 2014
450 MHz/600MHz, MCU with ARM Cortex®-R4F and -M3*1, on-chip FPU, 747/996 DMIPS, up to 1
Mbyte of on-chip extended SRAM, Ethernet MAC, EtherCAT*1, USB 2.0 high-speed, CAN, various
communications interfaces such as an SPI multi-I/O bus controller, ∆Σ interface, safety functions,
encoder interfaces*1, and security functions*1
Features
On-chip 32-bit ARM Cortex-R4F processor
High-speed realtime control with maximum operating frequency of
450/600 MHz
Capable of 747/996 DMIPS (in operation at 450/600 MHz)
On-chip 32-bit ARM Cortex-R4F (revision r1p4)
Tightly coupled memory (TCM) with ECC: 512 Kbytes/32 Kbytes
Instruction cache/data cache with ECC: 8 Kbytes per cache
High-speed interrupt
The FPU supports addition, subtraction, multiplication, division,
multiply-and-accumulate, and square-root operations at single-
precision and double-precision.
Harvard architecture with 8-stage pipeline
Supports the memory protection unit (MPU)
ARM CoreSight architecture, includes support for debugging
through JTAG and SWD interfaces
(Oinn-pcrhoidpu3c2ts-biint cAoRrpMoCraotrintegxa-Mn3Rp-IrNoceensgsinoer )
150-MHz operating frequency
On-chip 32-bit ARM Cortex-M3 (revision r2p1)
RISC Harvard architecture with 3-stage pipeline
Supports the memory protection unit (MPU)
Low power consumption
Standby mode, sleep mode, and module stop function
On-chip extended SRAM
Up to 1 Mbyte of the on-chip extended SRAM with ECC
150 MHz
Data transfer
DMAC: 16 channels × 2 units
DMAC for the Ethernet controller: 1 channel
Event link controller
Module operations can be started by event signals rather than by
interrupt handlers.
Linked operation of modules is available even while the CPU is in
the sleep state.
Reset and power supply voltage control
Four reset sources including a pin reset
Dual power-voltage configuration: 3.3 V (I/O unit), 1.2 V
(internal)
Clock functions
External clock/oscillator input frequency: 25 MHz
CPU clock frequency: Up to 450/600 MHz
Low-speed on-chip oscillator (LOCO): 240 kHz
Independent watchdog timer
Operated by a clock signal obtained by frequency-dividing the
clock signal from the low-speed on-chip oscillator: Up to 120 kHz
Safety functions
Register write protection, input clock oscillation stop detection,
CRC, IWDTa, and A/D self-diagnosis
An error control module is incorporated to generate a pin signal
output, interrupt, or internal reset in response to errors originating
in the various modules.
Security functions (optional)*2
Boot mode with security through encryption
Encoder interfaces (optional)*3
EnDat 2.2 and BiSS-compliant interfaces
PRBG0320GA-A 17×17mm, 0.8-mm pitch
PLQP0176LD-A 20 x 20mm, 0.4-mm pitch
Various communications interfaces
Ethernet
- EtherCAT slave controller: 2 ports (for products incorporating an
R-IN engine)
- Ether-MAC: 1 port (without the switching function)
or
- Ether-MAC: 1 port (2 ports with the switching function)
USB 2.0 high-speed host/function : 1 channel
CAN (compliant with ISO11898-1): 2 channels (max.)
SCIFA with 16-byte transmission and reception FIFOs: 5 channels
I2C bus interface: 2 channels for transfer at up to 400 kbps
RSPIa: 4 channels
SPIBSC: Provides a single interface for multi-I/O compatible
serial flash memory
External address space
Buses for high-speed data transfer at 75 MHz (max.)
Support for up to 6 CS areas
8-, 16-, or 32-bit bus space is selectable per area
Up to 33 extended-function timers
16-bit TPUa (12 channels), MTU3a (9 channels), GPTa (4
channels): Input capture, output compare, PWM waveform output
16-bit CMT (6 channels), 32-bit CMTW (2 channels)
Serial sound interface (1 channel)
■ ∆Σ interface
Up to 4 ΔΣ modulators are connectable externally.
12-bit A/D converters
12 bits × 2 units (max.)
(8 channels for unit 0; 16 channels for unit 1)
Self diagnosis
Detection of analog input disconnection
Temperature sensor for measuring temperature
within the chip
General-purpose I/O ports
5-V tolerance, open drain, input pull-up
Multi-function pin controller
The locations of input/output functions for peripheral modules are
selectable from among multiple pins.
Operating temperature range
Tj = -40°C to +125°C
Note 1.
Note 2.
Note 3.
Optional
Details of these optional functions will only be given after completion of a binding non-disclosure agreement. For details, contact our sales
representative.
For details, contact our sales representative.
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 1 of 51






R01DS0228EJ0060 Datasheet, Funktion
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1. Overview
Table 1.1
Outline of Specifications (5 / 7)
Classification Module/Function
Communication Ethernet MAC
function
(ETHERC)
Ethernet switch
EtherCAT Slave
Controller (ECATC) *2
USB 2.0 HS host/
function module
Description
1 Port
IEEE802.3 is supported
10BASE and 100BASE are supported
Full duplex and half duplex are supported
Automatic pause packet transmission function
Auto broadcast suspension function by the pause packet reception
MII/RMII interface is supported
2-port PHY interfaces
IEEE802.3
10BASE, 100BASE
Full and half duplex
Hardware switching, lookup, and filtering
QoS with frame prioritization
Priority control based on VLAN Priority (IEEE802.1q), which enables priority
reassignment
Classification and priority assignment based on IPv4 DiffServ Code Point Field, IPv6
Class of Service
Queue with four priority levels
Multicasting and broadcasting
VLAN frame
IEEE1588 timer module
Cut-through and hub features
Device level ring (DLR)
1 channel (2 ports) *3
EtherCAT Slave Controller IP core (made by Beckhoff Automation GmbH) implemented
1 port
Compliance with the USB 2.0 specification
Transfer rate
High speed (480 Mbps), full speed (12 Mbps)
Communications buffer
Incorporates 1 Kbyte of RAM for host mode
Incorporates 8 Kbytes of RAM for function mode
Serial communication
interface with FIFO
(SCIFA)
5 channels
Serial communications modes: Asynchronous, clock synchronous
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Both the transmission and reception sections are equipped with 16-byte FIFO buffers,
allowing continuous transmission and reception.
Bit rate modulation
I2C bus interface (RIICa)
2 channels
I2C bus format
Supports the multi-master
Max. transfer rate: 400 kbps
Event linking by the ELC
CAN module (RSCAN)
2 channels
Compliance with the ISO11898-1 specification (standard frame and extended frame)
Message buffers
Max. 64 x 2 channels of receive message buffers, which are used by all channels
16 transmit message buffers per channel
Max. transfer rate: 1 Mbps
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 6 of 51

6 Page







R01DS0228EJ0060 pdf, datenblatt
Under development Preliminary document
Specifications in this document are tentative and subject to change.
RZ/T1 Group
1.3 Block Diagram
Figure 1.1 shows a block diagram of a 320-pin device.
1. Overview
MTU3a × 9 channels
GPTA × 4 channels
SCIFA × 5 channels
RSPIa × 4 channels
ECATC *1
ETHERC × 3 ports
On-chip
extended
SRAM with
ECC
Cortex-M3*1
NVIC
MPU
USB
× 1 port
Cortex-R4F
VIC
MPU
TCM
Clock
generation
circuit
DMAC ×
16 channels
(unit 0)
DMAC ×
16 channels
(unit 1)
ELC
TPUa × 6 channels (unit 0)
TPUa × 6 channels (unit 1)
POE3
PPG (unit 0)
PPG (unit 1)
CMT × 2 channels (unit 0)
CMT × 2 channels (unit 1)
CMT × 2 channels (unit 2)
CMTW × 1 channel (unit 0)
CMTW × 1 channel (unit 1)
WDTA×1ch
Products incorporating an R-IN engine: WDTA×2ch
IWDTa
RIIC × 2 channels
RSCAN × 2 channels
SSI
DSMIF × 4 channels
CRC
CLMA
DOC
ECM
12-bit A/D converter × 8 channels (unit 0)
12-bit A/D converter × 16 channels (unit 1)
Temperature sensor
SPIBSC
BSC
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Port H
Port J
Port K
Port L
Port M
Port N
Port P
Port R
Port S
Port T
Port U
ETHERC:
ECATC:
DMAC:
BSC:
SPIBSC:
WDTA:
IWDTa:
SCIFA:
RSPIa:
USB:
VIC:
NVIC:
MPU:
ELC:
TPUa:
MTU3a:
Ethernet controller
EtherCAT slave contoller
DMA controller
Bus state controller
SPI multi I/O bus controller
Watchdog timer
Independent watchdog timer
Serial communication interface with FIFO
Serial peripheral interface
USB 2.0 HS host/function module
Vector interrupt controller
Nested-type vector interrupt controller
Memory protection unit
Event link controller
16-bit timer pulse unit
Multi-function timer pulse unit 3
POE3:
GPTa:
PPG:
CMT:
CMTW:
RIICa:
RSCAN:
SSI:
DSMIF:
CRC:
CLMA:
DOC:
ECM:
Port output enable 3
General-purpose PWM timer
Programmable pulse generator
Compare match timer
Compare match timer W
I2C bus interface
CAN module
Serial sound interface
∆Σ interface
CRC (cyclic redundancy check) calculator
Clock monitor circuit
Data operation circuit
Error control module
Note 1. Only included in products incorporating an R-IN
engine
Figure 1.1
Block Diagram
R01DS0228EJ0060 Rev.0.60
Nov 14, 2014
Page 12 of 51

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