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EN6360QA Schematic ( PDF Datasheet ) - Altera

Teilenummer EN6360QA
Beschreibung 8A PowerSoC Highly Integrated Synchronous DC-DC Buck
Hersteller Altera
Logo Altera Logo 




Gesamt 24 Seiten
EN6360QA Datasheet, Funktion
Enpirion® Power Datasheet
EN6360QA 8A PowerSoC
Highly Integrated Synchronous
DC-DC Buck with Integrated Inductor
Description
The EN6360QA is an 8A Power System on a Chip
(PowerSoC) DC to DC converter with an integrated
inductor, PWM controller, MOSFETs and
compensation to provide the smallest solution size in
an 8x11x3mm 68 pin QFN module. The EN6360QA is
AEC-Q100 qualified for automotive applications and
is specifically designed to meet the precise voltage
and fast transient requirements of high-performance,
low-power processor, DSP, FPGA, memory boards
and system level applications in distributed power
architecture. The EN6360QA features switching
frequency synchronization with an external clock or
other EN6360QAs for parallel operation. Other
features include precision enable threshold, pre-bias
monotonic start-up, and programmable soft-start. The
device’s advanced circuit techniques, ultra high
switching frequency, and proprietary integrated
inductor technology deliver high-quality, ultra
compact, non-isolated DC-DC conversion.
The Altera Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity by
offering greatly simplified board design, layout and
manufacturing requirements. All Altera Enpirion
products are RoHS compliant and lead-free
manufacturing environment compatible.
Features
High Efficiency (Up to 96%)
-40°C to +105°C Ambient Temperature Range
AEC-Q100 Qualified for Automotive Applications
CISPR 25 §6.6 / ISO11452-5 Compliant
Excellent Ripple and EMI Performance
Up to 8A Continuous Operating Current
Input Voltage Range (2.5V to 6.6V)
Frequency Synchronization (Clock or Primary)
2% VOUT Accuracy (Over Line/Load/Temperature)
Optimized Total Solution Size (210mm2)
Precision Enable Threshold for Sequencing
Programmable Soft-Start
Master/Slave Configuration for Parallel Operation
Thermal Shutdown, Over-Current, Short Circuit,
and Under-Voltage Protection
RoHS Compliant, MSL Level 3, 260°C Reflow
Applications
Automotive Applications
Point of Load Regulation for Low-Power, ASICs
Multi-Core and Communication Processors, DSPs,
FPGAs and Distributed Power Architectures
High Efficiency 12V Intermediate Bus Architectures
Beat Frequency/Noise Sensitive Applications
VIN
2x
22µF
1206
PVIN
VOUT
ENABLE
EN6360QA
AVIN
SS VFB
VOUT
2x
47µF
1210
RA CA
R1
15nF
PGND
PGND
AGND FQADJ
RFQADJ
RB
Figure 1. Simplified Applications Circuit
100
90
80
70
60
50
40
30
20
10
0
0
Efficiency vs. Output Current
CONDITIONS
VIN = 5.0V
VOUT = 3.3V
VOUT = 1.2V
Actual Solution Size
210mm2
123456
OUTPUT CURRENT (A)
7
8
Figure 2. Highest Efficiency in Smallest Solution Size
10396
October 7, 2014
www.altera.com/enpirion
Rev A






EN6360QA Datasheet, Funktion
EN6360QA
PARAMETER
POK Deglitch Delay
SYMBOL
TEST CONDITIONS
Falling Edge Deglitch Delay After
Output Crossing 90% level.
FSW=1.2 MHz
MIN TYP MAX UNITS
213 µs
VPOK Logic Low level
VPOK Logic high level
POK Internal pull-up
resistor
With 4mA Current Sink into POK Pin
0.4
VIN
94
V
V
k
Current Balance
VOUT Rise Time
Accuracy
IOUT
TRISE
(Note 4)
With 2 to 4 Converters in Parallel,
the Difference Between Nominal
and Actual Current Levels.
VIN<50mV; RTRACE< 10 m,
Iload= # Converter * IMAX
tRISE [ms] = CSS [nF] x 0.065;
10nF ≤ CSS 30nF;
(Note 5 and Note 6)
+/-10
-25 +25
%
%
ENABLE Logic High
ENABLE Logic Low
ENABLE Pin Current
M/S Ternary Pin Logic
Low
VENABLE_HIGH
VENABLE_LOW
IEN
VT-LOW
2.5V ≤ VIN ≤ 6.6V;
VIN = 6.6V
Tie M/S Pin to GND
1.2 VIN
0 0.8
50
0 0.7
V
V
µA
V
M/S Ternary Pin Logic
Float
VT-FLOAT
M/S Pin is Open
1.1 1.4 V
M/S Ternary Pin Logic
Hi (Note 7)
VT-HIGH
Ternary Pin Input
Current
ITERN
Binary Pin Logic Low
Threshold
VB-LOW
Pull Up to VIN through an external
resistor REXT . Refer to Figure 7.
2.5V VIN ≤ 4V, REXT = 15kΩ
4V < VIN 6.6V, REXT = 51kΩ
ENABLE, S_IN
1.8
V
117
88
µA
0.8 V
Binary Pin Logic High
Threshold
VB-HIGH
ENABLE, S_IN
1.8
V
S_OUT Low Level
S_OUT High Level
VS_OUT_LOW
VS_OUT_HIGH
0.4 V
2.0 V
Note 3: POK threshold when VOUT is rising is nominally 92%. This threshold is 90% when VOUT is falling. After crossing
the 90% level, there is a 256 clock cycle (~213µs at 1.2 MHz) delay before POK is de-asserted. The 90% and 92% levels
are nominal values. Expect these thresholds to vary by ±3%.
Note 4: Parameter not production tested but is guaranteed by design.
Note 5: Rise time calculation begins when AVIN > VUVLO and ENABLE = HIGH.
Note 6: VOUT Rise Time Accuracy does not include soft-start capacitor tolerance..
Note 7: M/S pin is ternary. Ternary pins have three logic levels: high, float, and low. This pin is meant to be strapped to
VIN through an external resistor, strapped to GND, or left floating. The state cannot be changed while the device is on.
10396
October 7, 2014
www.altera.com/enpirion, Page 6
Rev A

6 Page









EN6360QA pdf, datenblatt
Typical Performance Characteristics (Continued)
EN6360QA
Enable/Disable with POK
ENABLE
VOUT
POK
Load Transient from 0 to 8A
CONDITIONS
VIN = 6.2V
VOUT = 1.5V
CIN = 2 x 22µF (1206)
COUT = 2 x 47µF (1210)
VOUT
(AC Coupled)
LOAD
CONDITIONS
VIN = 5V, VOUT = 1.0V
LOAD = 5A, Css = 15nF
LOAD
Parallel Operation SW Waveforms
MASTER VSW
SLAVE 2 VSW
SLAVE 1 VSW
COMBINED LOAD(18A)
CONDITIONS
VIN = 5V
VOUT = 1.8V
LOAD = 18A
Parallel Operation Current Sharing
TOTAL LOAD = 18A
MASTER LOAD = 6A
SLAVE 2 LOAD = 6A
SLAVE 1 LOAD = 6A
CONDITIONS
VIN = 5V
VOUT = 1.8V
LOAD = 18A
10396
October 7, 2014
www.altera.com/enpirion, Page 12
Rev A

12 Page





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