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AD9785 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9785
Beschreibung Dual 12-/14-/16-Bit 800 MSPS DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9785 Datasheet, Funktion
Data Sheet
Dual 12-/14-/16-Bit 800 MSPS DAC
with Low Power 32-Bit Complex NCO
AD9785/AD9787/AD9788
FEATURES
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Low power, fine complex NCO allows carrier placement
anywhere in DAC bandwidth while adding <300 mW power
Auxiliary DACs allow I and Q gain matching and offset control
Includes programmable I and Q phase compensation
Internal digital upconversion capability
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
100-lead, exposed pad TQFP package
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM
Digital high or low IF synthesis
Transmit diversity
Wideband communications
LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9785/AD9787/AD9788 are 12-bit, 14-bit, and 16-bit,
high dynamic range TxDAC® devices, respectively, that provide
a sample rate of 800 MSPS, permitting multicarrier generation
up to the Nyquist frequency. Features are included for optimizing
direct conversion transmit applications, including complex
digital modulation, as well as gain, phase, and offset compens-
ation. The DAC outputs are optimized to interface seamlessly
with analog quadrature modulators, such as the ADL5375
family from Analog Devices, Inc. A serial peripheral interface
(SPI) provides for programming and readback of many internal
parameters. Full-scale output current can be programmed over
a range of 10 mA to 30 mA. The AD9785/AD9787/AD9788
family is manufactured on a 0.18 μm CMOS process and operates
from 1.8 V and 3.3 V supplies. It is enclosed in a 100-lead TQFP
package.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals from baseband
to high intermediate frequencies.
2. Proprietary DAC output switching technique enhances
dynamic performance.
3. CMOS data input interface with adjustable setup and hold.
4. Low power complex 32-bit numerically controlled
oscillators (NCOs).
COMPLEX I AND Q
DC
FPGA/ASIC/DSP
TYPICAL SIGNAL CHAIN
QUADRATURE
MODULATOR/
MIXER/
AMPLIFIER
DC
LO
DIGITAL INTERPOLATION FILTERS
I DAC
Q DAC
POST DAC
ANALOG FILTER
A
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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AD9785 Datasheet, Funktion
AD9785/AD9787/AD9788
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
AVDD33 to AGND, DGND, CGND
DVDD33, DVDD18, CVDD18
to AGND, DGND, CGND
AGND to DGND, CGND
DGND to AGND, CGND
CGND to AGND, DGND
I120, VREF, IPTAT to AGND
OUT1_P, OUT1_N, OUT2_P, OUT2_N,
AUX1_P, AUX1_N, AUX2_P,
AUX2_N to AGND
P1D[15] to P1D[0], P2D[15] to P2D[0]
to DGND
DATACLK, TXENABLE to DGND
REFCLK+, REFCLK−, RESET, IRQ,
PLL_LOCK, SYNC_O+, SYNC_O−,
SYNC_I+, SYNC_I− to CGND
RESET, IRQ, PLL_LOCK, SYNC_O+,
SYNC_O−, SYNC_I+, SYNC_I−,
SPI_CS, SCLK, SPI_SDIO, SPI_SDO
to DGND
Junction Temperature
Storage Temperature Range
Rating
−0.3 V to +3.6 V
−0.3 V to +2.1 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to AVDD33 + 0.3 V
−1.0 V to AVDD33 + 0.3 V
−0.3 V to DVDD33 + 0.3 V
−0.3 V to DVDD33 + 0.3 V
−0.3 V to CVDD18 + 0.3 V
−0.3 V to DVDD33 + 0.3 V
125°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Data Sheet
THERMAL RESISTANCE
For this 100-lead, thermally enhanced TQFP, the exposed pad
(EPAD) must be soldered to the ground plane. Note that these
specifications are valid with no airflow movement.
Table 5. Thermal Resistance
Resistance Unit
Conditions
θJA 19.1°C/W EPAD soldered. No airflow.
θJB 12.4°C/W EPAD soldered. No airflow.
θJC 7.1°C/W EPAD soldered. No airflow.
ESD CAUTION
Rev. B | Page 6 of 64

6 Page









AD9785 pdf, datenblatt
AD9785/AD9787/AD9788
Data Sheet
Pin No.
30
31
34
35
36
37
38, 61
39
40
41
42
45
46
47
48
49
50
51
52
55
56
57
58
59
62
63
65
66
67
68
69
70
71
73
74
75
76, 78, 80, 96, 98, 100
83
84
86
87
89
90
92
93
Mnemonic
P1D[4]
P1D[3]
P1D[2]
P1D[1]
P1D[0]
DATACLK
DVDD33
TXENABLE
P2D[15]
P2D[14]
P2D[13]
P2D[12]
P2D[11]
P2D[10]
P2D[9]
P2D[8]
P2D[7]
P2D[6]
P2D[5]
P2D[4]
P2D[3]
P2D[2]
P2D[1]
P2D[0]
SYNC_O−
SYNC_O+
PLL_LOCK
SPI_SDO
SPI_SDIO
SCLK
SPI_CS
RESET
IRQ
IPTAT
VREF
I120
AVDD33
OUT2_P
OUT2_N
AUX2_P
AUX2_N
AUX1_N
AUX1_P
OUT1_N
OUT1_P
EPAD
Description
Port 1, Data Input D4.
Port 1, Data Input D3.
Port 1, Data Input D2.
Port 1, Data Input D1.
Port 1, Data Input D0 (LSB).
Data Clock Output.
3.3 V Digital Supply.
Transmit Enable.
Port 2, Data Input D15 (MSB).
Port 2, Data Input D14.
Port 2, Data Input D13.
Port 2, Data Input D12.
Port 2, Data Input D11.
Port 2, Data Input D10.
Port 2, Data Input D9.
Port 2, Data Input D8.
Port 2, Data Input D7.
Port 2, Data Input D6.
Port 2, Data Input D5.
Port 2, Data Input D4.
Port 2, Data Input D3.
Port 2, Data Input D2.
Port 2, Data Input D1.
Port 2, Data Input D0 (LSB).
Differential Synchronization Output, Negative.
Differential Synchronization Output, Positive.
PLL Lock Indicator.
SPI Port Data Output.
SPI Port Data Input/Output.
SPI Port Clock.
SPI Port Chip Select Bar.
Reset, Active High.
Interrupt Request.
Factory Test Pin. Output current is proportional to absolute temperature, approximately 10 μA at
25°C with approximately 20 nA/°C slope. This pin should remain floating.
Voltage Reference Output.
120 μA Reference Current.
3.3 V Analog Supply.
Differential DAC Current Output, Positive, Channel 2.
Differential DAC Current Output, Negative, Channel 2.
Auxiliary DAC Current Output, Positive, Channel 2.
Auxiliary DAC Current Output, Negative, Channel 2.
Auxiliary DAC Current Output, Negative, Channel 1.
Auxiliary DAC Current Output, Positive, Channel 1.
Differential DAC Current Output, Negative, Channel 1.
Differential DAC Current Output, Positive, Channel 1.
Exposed Paddle. The EPAD is a conductive heat sink. Connect the EPAD to analog common (AGND).
Rev. B | Page 12 of 64

12 Page





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