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R1LP0408CSP-5SC Schematic ( PDF Datasheet ) - Renesas

Teilenummer R1LP0408CSP-5SC
Beschreibung 4M SRAM
Hersteller Renesas
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Gesamt 14 Seiten
R1LP0408CSP-5SC Datasheet, Funktion
R1LP0408C-C Series
4 M SRAM (512-kword × 8-bit)
REJ03C0077-0100Z
Rev. 1.00
Aug.01.2003
Description
The R1LP0408C-C is a 4-Mbit static RAM organized 512-kword × 8-bit. R1LP0408C-C Series has
realized higher density, higher performance and low power consumption by employing CMOS process
technology (6-transistor memory cell). The R1LP0408C-C Series offers low power standby power
dissipation; therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32-pin
TSOP II.
Features
Single 5 V supply: 5 V ± 10%
Access time: 55/70 ns (max)
Power dissipation:
Active: 10 mW/MHz (typ)
Standby: 4 µW (typ)
Completely static memory.
No clock or timing strobe required
Equal access and cycle times
Common data input and output.
Three state output
Directly TTL compatible.
All inputs and outputs
Battery backup operation.
Operating temperature: 20 to +70°C
Rev.1.00, Aug.01.2003, page 1 of 13






R1LP0408CSP-5SC Datasheet, Funktion
R1LP0408C-C Series
DC Characteristics
Parameter
Symbol Min Typ*1 Max Unit Test conditions
Input leakage current
Output leakage current
Operating current
Average operating current
|ILI|
|ILO|
ICC
ICC1
ICC2
Standby current
Standby current
to +70°C
to +40°C
20°C to +25°C
ISB
ISB1
ISB1
ISB1
  1 µA Vin = VSS to VCC
  1 µA CS# = VIH or OE# = VIH or
WE# = VIL or VI/O = VSS to VCC
1.5 3
mA CS# = VIL,
Others = VIH/ VIL, II/O = 0 mA
8
25 mA Min. cycle, duty = 100%,
CS# = VIL, Others = VIH/VIL
II/O = 0 mA
2
5 mA Cycle time = 1 µs,
duty = 100%,
II/O = 0 mA, CS# 0.2 V,
VIH VCC 0.2 V, VIL 0.2 V
0.1


0.5 mA
16*2 µA
8*3 µA
CS# = VIH
Vin 0 V, CS# VCC 0.2 V
1.0*2 10*2 µA
1.0*3 3*3 µA
0.8*2 10*2 µA
0.8*3 3*3 µA
Output low voltage
VOL   0.4 V IOL = 2.1 mA
Output high voltage
VOH 2.4   V IOH = 1.0 mA
VOH2 2.6   V IOH = 0.1 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. L version. (7LC)
3. SL version. (5SC)
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter
Symbol Min Typ Max
Input capacitance
Cin   8
Input/output capacitance
CI/O   10
Note: 1. This parameter is sampled and not 100% tested.
Unit
pF
pF
Test conditions
Vin = 0 V
VI/O = 0 V
Note
1
1
Rev.1.00, Aug.01.2003, page 6 of 13

6 Page









R1LP0408CSP-5SC pdf, datenblatt
R1LP0408C-C Series
Low VCC Data Retention Characteristics
(Ta = 20 to +70°C)
Parameter
Symbol Min Typ*4 Max Unit Test conditions*3
VCC for data retention
Data retention
to +70°C
current
to +40°C
20°C to +25°C
VDR
ICCDR*1
ICCDR*2
ICCDR*1
ICCDR*2
ICCDR*1
ICCDR*2
2


V CS# VCC 0.2 V, Vin 0 V
16 µA VCC = 3.0 V, Vin 0 V
CS# VCC 0.2 V
8
1.0 10 µA
1.0 3
0.8 10 µA
0.8 3
Chip deselect to data retention time
Operation recovery time
tCDR
tR
0   ns See retention waveform
tRC*5   ns
Notes: 1. This characteristic is guaranteed only for L version.
2. This characteristic is guaranteed only for SL version.
3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,
Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.
4. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
5. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (CS# Controlled)
VCC
4.5 V
tCDR
Data retention mode
tR
2.4 V
VDR
CS#
0V
CS# VCC 0.2 V
Rev.1.00, Aug.01.2003, page 12 of 13

12 Page





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