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PDF AA141TC01 Data sheet ( Hoja de datos )
| Número de pieza | AA141TC01 | |
| Descripción | WXGA Display Module | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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TENTATIVE
All information in this technical data sheet is tentative
and subject to change without notice.
14.1” WXGA
TECHNICAL SPECIFICATION
AA141TC01
MITSUBISHI ELECTRIC Corp.
MITSUBISHI Confidential
(1/26)
Date: Nov.8,’10
AA141TC01_02_00
1 page  
3. ABSOLUTE MAXIMUM RATINGS
ITEM
SYMBOL
MIN.
MAX
UNIT
Power Supply Voltage for LCD
VCC 0 4.0 V
Logic Input Voltage
VI −0.3 VCC+0.3 V
Backlight (LED) Current
IF 0 180 mA
Operation Temperature(Panel)
Note 1,2)
Top(Panel)
−20
70 °C
Operation Temperature(Ambient) Note 2)
Top(Ambient)
−20
70 °C
Storage Temperature
Note 2)
Tstg
−20
80 °C
[Note]
1) Measured at the center of active area and at the center of panel back surface
2) Top,Tstg ≤ 40°C : 90%RH max. without condensation
Top,Tstg > 40°C : Absolute humidity shall be less than the value of 90%RH at 40°C without
condensation.
4. ELECTRICAL CHARACTERISTICS
(1) TFT-LCD
ITEM
SYMBOL MIN.
Power Supply Voltages for LCD VCC
3.0
Power Supply Currents for LCD ICC
--
Permissive Input Ripple Voltage VRP
--
Logic Input Voltage
High
Low
VIH 0.8×VCC
VIL 0
*1) Power and signals sequence:
t1 ≤ 10 ms
0 < t2 ≤ 50 ms
0 < t3 ≤ 50 ms
200 ms ≤ t4
200 ms ≤ t5
0 ≤ t6
TYP.
3.3
570
--
--
--
Ambient temperature: Ta = 25°C
MAX. UNIT
Remarks
3.6 V
*1)
960 mA
*2)
100 mVp-p VCC = +3.3V
VCC
V
MODE
0.2×VCC V
MODE
LCD Power Supply
0.9VCC
Logic Signal
0.1VCC
VCC
data
0.9VCC
0.1VCC 0.1VCC
t1 t2
t3 t4
Backlight Power Supply
t5 t6
data: RGB DATA, DCLK, DENA, MODE
MITSUBISHI Confidential
(5/26)
AA141TC01_02_00
5 Page 
6. INTERFACE TIMING
LVDS transmitter input signal
(1) Timing Specifications
ITEM
SYMBOL MIN
TYP
MAX
UNIT
Frequency
DCLK Period
fCLK
tCLK
50
12.5
71
14.1
80
20
MHz
ns
Active Time
tHA
1280
1280
1280
tCLK
Blanking Time
Horizontal
Frequency
tHB
fH
20 160
42.4 49.4
--
60
tCLK
kHz
DENA
Period
Active Time
tH 16.6 20.3 23.6
tVA 800 800 800
μs
tH
Vertical Blanking Time
tVB
3
23 --
tH
Frequency
fV 55 60 70 Hz
Period
tV 14.3 16.7 18.2 ms
[Note]
1) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
2) DCLK should appear during all invalid period.
3) LVDS timing follows the timing specifications of LVDS receiver IC: THC63LVDF84B(Thine).
4) In case of blanking time fluctuation, please satisfy following condition.
tVBn > tVBn-1 − 3(tH)
MITSUBISHI Confidential
(11/26)
AA141TC01_02_00
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet AA141TC01.PDF ] | |
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