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PDF WM8505 Data sheet ( Hoja de datos )

Número de pieza WM8505
Descripción Application Processor
Fabricantes WonderMedia　
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Data Sheet
WM8505
Application Processor
September 23, 2009
Revision 0.71

1 page




WM8505 pdf
Data Sheet
WM8505 Application Processor
iv
List of Figures
Figure 1 - WM8505 System Block Diagram......................................................................................5
Figure 2 - WM8505 Software Architecture .......................................................................................6
Figure 3 - WM8505 Ball Diagram – Left (Top View) ..........................................................................7
Figure 4 - WM8505 CIR Diagram ............................................................................................... 146
Figure 5 - WM8505 Power Domains............................................................................................ 177
Figure 6 - Power Modes and Power Consumption ......................................................................... 179
Figure 7 - Power On Sequence w/ Suspend Power........................................................................ 182
Figure 8 - Power On Sequence w/ Non-Suspend Power ................................................................. 182
Figure 9 - 27 MHz Crystal Network............................................................................................. 185
Figure 10 - Internal Clock Generation of 25 MHz Clock Network..................................................... 186
Figure 11 - RTC Crystal Network ................................................................................................ 187
Figure 12 - RTCXI/RTCXO Connection as RTC not Needed ............................................................. 187
Figure 13 - AHB DMA Controller in System.................................................................................. 188
Figure 14 - AHB DMA Controller Internal Block Diagram ............................................................... 188
Figure 15 - DMA Rotating Priority Scheme .................................................................................. 193
Figure 16 - Audio Controller Module Block Diagram ...................................................................... 198
Figure 17 - UART Serial Data Transfer Format.............................................................................. 201
Figure 18 - I2C Bus Byte Transfer............................................................................................... 206
Figure 19 - DATA Timing Diagram .............................................................................................. 212
Figure 20 - Command Timing Dagram ........................................................................................ 213
Figure 21 - DQ/DQS Read Timing Diagram.................................................................................. 213
Figure 22 - DQ/DQS/DM Write Timing Diagram ........................................................................... 214
Figure 23 - Serial Flash Memory Controller Interface Timing.......................................................... 215
Figure 24 - Ethernet MAC Interface Timing – Clock ...................................................................... 216
Figure 25 - Ethernet MAC Interface Timing –Transmit Timing......................................................... 216
Figure 26 - Ethernet MAC Interface Timing –Setup & Hold Time..................................................... 216
Figure 27 - RevMII Connection Diagram ..................................................................................... 217
Figure 28 - Ethernet MAC Interface Timing –Setup & Hold Time..................................................... 217
Figure 29 - Ethernet MAC Interface Timing –Setup & Hold Time..................................................... 217
Figure 30 - KBDC Interface Timing – Sending Data to External Keyboard/mouse ............................. 218
Figure 31 - KBDC Interface Timing – Reveiving Data from External Keyboard/mouse ....................... 218
Figure 32 - NAND Flash Interface Timing – Command Latch.......................................................... 219
Figure 33 - NAND Flash Interface Timing – Address Latch ............................................................. 219
Figure 34 - NAND Flash Interface Timing – Data Read .................................................................. 220
Figure 35 - Read Timing – Read Initial Cycle Timing in Asynchronous Read ..................................... 221
Figure 36 - Page Mode Read Timing in Asynchronous Mode ........................................................... 221
Figure 37 - Write Timing in Asynchronous Mode .......................................................................... 222
Figure 38 - Reset Timing .......................................................................................................... 223
Figure 39 - SD Interface Timing – Data Read .............................................................................. 224
Figure 40 - DVO Interface Timing .............................................................................................. 225
Figure 41 - CCIR-656/601 Input Pixel Data Timing....................................................................... 226
Figure 42 - CMOS Sensor Input Pixel Data Timing........................................................................ 226
Figure 43 - Audio I2S Interface Timing of Master Mode ................................................................. 227
Figure 44 - Audio I2S Interface Timing of Slave Mode ................................................................... 228
Figure 45 - UART Interface Timing ............................................................................................. 229
Figure 46 - SPI Interface Timing – SPI Master ............................................................................. 231
Figure 47 - SPI Interface Timing – SPI Slave ............................................................................... 232
Figure 48 - I2C Interface Timing ................................................................................................ 233
Figure 49 - AC97 Interface Timing ............................................................................................. 234
Figure 50 - ARM JTAG Interface Timing – Test Clock ..................................................................... 235
Figure 51 - ARM JTAG Interface Timing – Test Reset..................................................................... 235
Figure 52 - ARM JTAG Interface Timing – Test Data/Select ............................................................ 236
Figure 53 – WM8505 Mechanical Specification ............................................................................. 237

5 Page





WM8505 arduino
Data Sheet
WM8505 Application Processor
5
WM8505 System Overview
The WM8505 Application Processor is the SoC solution with superior networks and display capabilities that
specially tailored for cost-effective embedded multimedia devices. The WM8505 supports display resolution
up to 1024x600 and 10/100 Ethernet MAC. The WM8505 is a low power consumption SoC solution that
demands 1.8V for DDR2 SDRAM, and 3.3 V for other interfaces as operating power. The WM8505 integrates
multimedia features and functionalities, e.g. decoding popular audio/video streams, 2D graphics display,
and peripheral I/Os that are aiming to meet upcoming market demands as well as reduce customer’s total
BOM cost. The WM8505 is designed to deliver the state-of-the-art performance for applications such as
Networked Projector, Digital Signage, and Thin-Client Terminal.
The WM8505 Application Processor integrates all popular peripherals in an efficiently architected RISC
(reduced instruction set computer) platform. Figure 1 illustrates the system block diagram of
WonderMedia's WM8505 Application Processor.
Figure 1 - WM8505 System Block Diagram

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