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PDJ2108DEBG Schematic ( PDF Datasheet ) - Deutron Electronics

Teilenummer PDJ2108DEBG
Beschreibung 2G bits DDR3 SDRAM
Hersteller Deutron Electronics
Logo Deutron Electronics Logo 




Gesamt 70 Seiten
PDJ2108DEBG Datasheet, Funktion
DATA SHEET
2G bits DDR3 SDRAM
PDJ2108DEBG (256M words × 8 bits)
PDJ2116DEBG (128M words × 16 bits)
Specifications
Density: 2G bits
Organization:
32M words × 8 bits × 8 banks (PDJ2108DEBG)
16M words × 16 bits × 8 banks (EDJ2116DEBG)
Package:
78-ball FBGA (PDJ2108DEBG)
96-ball FBGA (PDJ2116DEBG)
Lead-free (RoHS compliant) and Halogen-free
Power supply: VDD, VDDQ = 1.5V ± 0.075V
Data rate
1600Mbps/1333Mbps (max.)
1KB page size (PDJ2108DEBG)
Row address: A0 to A14
Column address: A0 to A9
2KB page size (PDJ2116DEBG)
Row address: A0 to A13
Column address: A0 to A9
Eight internal banks for concurrent operation
Interface: SSTL_15
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
Burst type (BT):
Sequential (8, 4 with BC)
Interleave (8, 4 with BC)
/CAS Latency (CL): 6, 7, 8, 9, 10, 11
/CAS Write Latency (CWL): 5, 6, 7, 8
Precharge: auto precharge option for each burst
access
Driver strength: RZQ/7, RZQ/6, RZQ/5 (RZQ = 240Ω)
Refresh: auto-refresh, self-refresh
Refresh cycles
Average refresh period
7.8μs at 0°C TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
Double-data-rate architecture: two data transfers per
clock cycle
The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted /CAS by programmable additive latency for
better command and data bus efficiency
On-Die Termination (ODT) for better signal quality
Synchronous ODT
Dynamic ODT
Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined pattern
read out
ZQ calibration for DQ drive and ODT
/RESET pin for Power-up sequence and reset
function
SRT range:
Normal/extended
Programmable Output driver impedance control
Seamless BL4 access with bank-grouping
Document Ver. 4.1 Deutron Electronics Corp.






PDJ2108DEBG Datasheet, Funktion
PDJ2108DEBG, PDJ2116DEBG
DDR3 SDRAM Mode Register 1 [MR1] ...................................................................................................... 72
DDR3 SDRAM Mode Register 2 [MR2] ...................................................................................................... 73
DDR3 SDRAM Mode Register 3 [MR3] ...................................................................................................... 74
Burst Length (MR0) .................................................................................................................................... 75
Burst Type (MR0) ....................................................................................................................................... 75
DLL Enable (MR1) ...................................................................................................................................... 76
DLL-off Mode .............................................................................................................................................. 76
DLL on/off switching procedure .................................................................................................................. 77
Additive Latency (MR1)............................................................................................................................... 79
Write Leveling (MR1) .................................................................................................................................. 80
TDQS, /TDQS function (MR1) .................................................................................................................... 83
Extended Temperature Usage (MR2) ......................................................................................................... 84
Multi Purpose Register (MR3)..................................................................................................................... 86
Operation of the DDR3 SDRAM ..................................................................................................................94
Read Timing Definition................................................................................................................................ 94
Read Operation .......................................................................................................................................... 98
Write Timing Definition.............................................................................................................................. 105
Write Operation......................................................................................................................................... 106
Write Timing Violations ............................................................................................................................. 112
Write Data Mask ....................................................................................................................................... 113
Precharge ................................................................................................................................................. 114
Auto Precharge Operation ........................................................................................................................ 115
Auto-Refresh............................................................................................................................................. 116
Self-Refresh.............................................................................................................................................. 117
Power-Down Mode ................................................................................................................................... 119
Input Clock Frequency Change during Precharge Power-Down............................................................... 126
On-Die Termination (ODT)........................................................................................................................ 127
ZQ Calibration........................................................................................................................................... 139
Addendum: MIRA DDR3 SDRAM Special Feature, Seamless BL4 Access with Bank-Grouping ...........141
Background............................................................................................................................................... 141
Solution..................................................................................................................................................... 143
Seamless BL4 Access with Bank-Grouping Details.................................................................................. 146
AC Specification Comparison Table for Bank-Grouping Feature Enabled/Disabled................................. 148
Timing Diagram with Bank-Grouping Feature Enabled (MR3 bit A11 = 1)................................................ 150
Package Drawing ......................................................................................................................................165
78-ball FBGA ............................................................................................................................................ 165
96-ball FBGA ............................................................................................................................................ 166
Recommended Soldering Conditions........................................................................................................167
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PDJ2108DEBG pdf, datenblatt
PDJ2108DEBG, PDJ2116DEBG
[Data Setup and Hold Base-Values]
DDR3-1333
DDR3-1600
Unit Reference
tDS(base) AC175
ps VIH/VIL(AC)
tDS(base) AC150
30
10
ps VIH/VIL(AC)
tDH(base) DC100
65
45
Note: 1 AC/DC referenced for 1V/ns DQ slew rate and 2V/ns DQS slew rate
ps VIH/VIL(DC)
[Derating Values of tDS/tDH AC/DC based, AC150 (DDR3-1333, 1600)]
ΔtDS, ΔtDH derating in [ps] AC/DC based
DQS, /DQS differential slew rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH Unit
2.0 +75 +50 +75 +50 +75 +50 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ps
1.5 +50 +34 +50 +34 +50 +34 +58 +42 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ps
1.0 0 0 0 0 0 0 +8 +8 +16 +16 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ps
DQ 0.9 ⎯ ⎯ 0
4 0
slew
rate 0.8 ⎯ ⎯ ⎯ ⎯ 0
4 +8 +4 +16 +12 +24 +20 ⎯ ⎯ ⎯ ⎯ ps
10 +8 2 +16 +6 +24 +14 +32 +24 ⎯ ⎯ ps
(V/ns) 0.7 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ +8 8 +16 0
+24 +8 +32 +18 +40 +34 ps
0.6 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ +15 10 +23 2 +31 +8 +39 +24 ps
0.5 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ +14 16 +22 6 +30 +10 ps
0.4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ +7 26 +15 10 ps
[Required time tVAC above VIH(AC) {below VIL(AC)} for valid transition]
DDR3-1333, 1600 (AC150)
tVAC [ps]
Slew rate (V/ns)
min.
max.
>2.0 175
2.0 170
1.5 167
1.0 163
0.9 162
0.8 161
0.7 159
0.6 155
0.5 150
<0.5 150
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