EDE1108AJBG Datasheet PDF - Elpida Memory
| Part Number | EDE1108AJBG | |
| Description | 1G bits DDR2 SDRAM | |
| Manufacturers | Elpida Memory | |
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DATA SHEET
1G bits DDR2 SDRAM
EDE1108AJBG (128M words × 8 bits)
EDE1116AJBG (64M words × 16 bits)
Specifications
• Density: 1G bits
• Organization
16M words × 8 bits × 8 banks (EDE1108AJBG)
8M words × 16 bits × 8 banks (EDE1116AJBG)
• Package
60-ball FBGA (EDE1108AJBG)
84-ball FBGA (EDE1116AJBG)
Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Data rate
800Mbps (max.)
• 1KB page size (EDE1108AJBG)
Row address: A0 to A13
Column address: A0 to A9
• 2KB page size (EDE1116AJBG)
Row address: A0 to A12
Column address: A0 to A9
• Eight internal banks for concurrent operation
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• Burst type (BT):
Sequential (4, 8)
Interleave (4, 8)
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst
access
• Driver strength: normal, weak
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
• /DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation
• Off-Chip Driver (OCD) impedance adjustment is not
supported.
Document No. E1732E21 (Ver.2.1)
Date Published September 2011 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2010-2011
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EDE1108AJBG, EDE1116AJBG
Electrical Specifications
• All voltages are referenced to VSS (GND)
• Execute power-up and Initialization sequence before proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit Notes
Power supply voltage
VDD
−1.0 to +2.3
V1
Power supply voltage for output
VDDQ
−0.5 to +2.3
V1
Input voltage
VIN −0.5 to +2.3
V1
Output voltage
VOUT
−0.5 to +2.3
V1
Storage temperature
Tstg −55 to +100
°C 1, 2
Power dissipation
PD 1.0
W1
Short circuit output current
IOUT
50
mA 1
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage temperature is the case surface temperature on the center/top side of the DRAM.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Operating Temperature Condition
Parameter
Symbol
Rating
Unit Notes
Operating case temperature
TC
0 to +95
°C 1, 2
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. Supporting 0°C to +85°C with full AC and DC specifications.
Supporting 0°C to +85°C and being able to extend to +95°C with doubling auto-refresh commands in
frequency to a 32ms period (tREFI = 3.9µs) and higher temperature self-refresh entry via A7 "1" on
EMRS (2).
Data Sheet E1732E21 (Ver.2.1)
5
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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