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DCR022405P-U Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer DCR022405P-U
Beschreibung REGULATED DC/DC CONVERTERS
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 12 Seiten
DCR022405P-U Datasheet, Funktion
DCR02 SERIES
SBVS028A − DECEMBER 2000 − REVISED APRIL 2004
Miniature, 2W Isolated
REGULATED DC/DC CONVERTERS
FEATURES
D UL1950 Recognized
D DIP-18 and SO-10 Packages
D 55W/in3 (3.3W/cm3) Power Density
D Device-to-Device Synchronization
D Thermal Protection
D 1000Vrms Isolation
D 400kHz Switching
D 125 FITS at 55°C
D Short-Circuit Protection
D 12V, 24V Inputs
D 5V Outputs
APPLICATIONS
D Point-of-Use Power Conversion
D Digital Interface Power
D Ground Loop Elimination
D Power-Supply Noise Reduction
DESCRIPTION
The DCR02 family is a series of high-efficiency,
input-isolated, output-regulated DC/DC converters. In
addition to 2W nominal, galvanically-isolated output power
capability, this range of converters offers very low output
noise and high accuracy.
The DCR02 family is implemented in standard molded IC
packaging, providing standard JEDEC outlines suitable
for high-volume assembly.
The DCR is manufactured using the same technology as
standard IC packages, thereby achieving very high
reliability.
SYNC
VREC
VS
In p u t
C o n tro lle r
LDO
R egulator
ENABLE
ERROR
VOUT
0VIN
0VOUT
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semiconductor products and disclaimers thereto appears at the end of this data sheet.
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PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2000−2004, Texas Instruments Incorporated
www.ti.com






DCR022405P-U Datasheet, Funktion
DCR02 SERIES
SBVS028A − DECEMBER 2000 − REVISED APRIL 2004
ADDITIONAL FUNCTIONS
DISABLE/ENABLE
The DCR02 can be disabled or enabled by driving the
SYNC pin using an open drain CMOS gate. If the SYNC
pin is pulled low, the DCR02 will be disabled. The disable
time depends upon the external loading. The internal
disable function is implemented in 2µs. Removal of the pull
down will enable the DCR02.
Capacitance loading on the SYNC pin should be
minimized in order to prevent a reduction in the internal
oscillator frequency. See application report SBAA035 for
information on how to nullify the effects of additional
capacitance on the SYNC pin. The oscillator frequency
can be measured at VREC, as this is the fundamental
frequency of the ripple component.
OUTPUT ENABLE/DISABLE
The regulated output of the DCR02 can be disabled by
pulling the ENABLE pin low (by connecting ENABLE to
0VOUT). Holding the ENABLE pin high (connect ENABLE
to VREC) enables the regulated output voltage, thus
allowing the output to be controlled from the isolated side,
as shown in Figure 1.
ERROR FLAG
The DCR02 has an ERROR pin which provides a power
good flag, as long as the internal regulator is in regulation.
www.ti.com
DECOUPLING
Ripple Reduction
Due to the very low forward resistance of the DMOS
switching transistors, high-current demands are placed
upon the input supply for a short time. By placing a good
quality low ESR 2.2µF ceramic capacitor close to the IC
supply input pins, the effects on the power supply can be
minimized.
The high switching frequency of 400kHz allows relatively
small values of capacitors to be used for filtering the
rectified output voltage. A good quality, low ESR 1µF
ceramic capacitor placed close to the VREC pin and output
ground will reduce the ripple.
It is not recommended that the DCR02 be fitted using an
IC socket because this degrades performance.
The output at VREC is full wave rectified and produces a
ripple of 800kHz.
It is recommended that a 0.1µF low ESR ceramic capacitor
be connected close to the output pin and ground to reduce
noise on the output. The capacitor values listed are
minimum values. If lower ripple is required, the ceramic
filter capacitor should be increased in value to 2.2µF.
NOTE: As with all switching power supplies, the best
performance is only obtained with low ESR ceramic
capacitors connected close to the respective buses. If low
ESR ceramic capacitors are not used, the ESR will generate
a voltage drop when the capacitor is supplying the load
power. Often a larger capacitor is chosen for this purpose
when a low ESR smaller capacitance performs just as well.
U1
VIN VS
VOUT
RERR
10k
VO1
ERROR
ERROR
CIN(1)
SYNC
DCR 02
VREC
ENABLE
REN
10k
CFILTER
1µF
COUT
0.1µF
0V 0V
SW1
0VOUT
(see text)
NOTE: (1) Required 2.2µF low ESR ceramic capacitor.
Figure 1. DCR02 with a Single Output
6

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DCR022405P-U pdf, datenblatt
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DSP
Interface
Logic
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logic.ti.com
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Applications
Audio
Automotive
Broadband
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Military
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