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R1LP5256ESP-7SR Schematic ( PDF Datasheet ) - Renesas

Teilenummer R1LP5256ESP-7SR
Beschreibung 256Kb Advanced LPSRAM
Hersteller Renesas
Logo Renesas Logo 




Gesamt 15 Seiten
R1LP5256ESP-7SR Datasheet, Funktion
R1LP5256E Series
256Kb Advanced LPSRAM (32k word x 8bit)
R10DS0070EJ0100
Rev.1.00
2011.04.13
Description
The R1LP5256E Series is a family of low voltage 256-Kbit static RAMs organized as 32,768-word by 8-bit, fabricated
by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1LP5256E Series has realized higher
density, higher performance and low power consumption. The R1LP5256E Series is suitable for memory applications
where a simple interfacing, battery operating and battery backup are the important design objectives. It has been
packaged in 28-pin SOP and 28-pin TSOP.
Features
Single 4.5V~5.5V power supply
Small stand-by current: 1µA (5.0V, typical)
No clocks, No refresh
All inputs and outputs are TTL compatible.
Easy memory expansion by CS#
Common Data I/O
Three-state outputs: OR-tie Capability
OE# prevents data contention on the I/O bus
Ordering Information
Orderable Part Name
R1LP5256ESP-5SR#B0
R1LP5256ESP-5SI#B0
Access
time
55 ns
Temperature
Range
0 ~ +70°C
-40 ~ +85°C
R1LP5256ESP-7SR#B0
R1LP5256ESP-7SI#B0
R1LP5256ESP-5SR#S0
R1LP5256ESP-5SI#S0
R1LP5256ESP-7SR#S0
R1LP5256ESP-7SI#S0
R1LP5256ESA-5SR#B0
R1LP5256ESA-5SI#B0
70 ns
55 ns
70 ns
55 ns
0 ~ +70°C
-40 ~ +85°C
0 ~ +70°C
-40 ~ +85°C
0 ~ +70°C
-40 ~ +85°C
0 ~ +70°C
-40 ~ +85°C
R1LP5256ESA-7SR#B0
R1LP5256ESA-7SI#B0
R1LP5256ESA-5SR#S0
R1LP5256ESA-5SI#S0
R1LP5256ESA-7SR#S0
R1LP5256ESA-7SI#S0
70 ns
55 ns
70 ns
0 ~ +70°C
-40 ~ +85°C
0 ~ +70°C
-40 ~ +85°C
0 ~ +70°C
-40 ~ +85°C
Package
450-mil 28-pin
plastic SOP
PRSP0028DB-B
(28P2W-C)
8mm×13.4mm 28-pin
plastic TSOP
(normal-bend type)
PTSA0028ZA-A
(28P2C-A)
Shipping
Container
Quantity
Tube
Max. 30pcs/Tube
Max. 300pcs/Inner Bag
Max. 1200pcs/Inner Box
Embossed
tape
1000pcs/Reel
Tray
Max. 234pcs/Tray
Max. 1872pcs/Inner Box
Embossed
tape
1000pcs/Reel
R10DS0070EJ0100 Rev.1.00
2011.04.13
Page 1 of 13






R1LP5256ESP-7SR Datasheet, Funktion
R1LP5256E Series
Capacitance
(Vcc = 4.5V ~ 5.5V, f = 1MHz, Ta = 0 ~ +70°C / -40 ~ +85°C*2)
Parameter
Symbol Min. Typ. Max. Unit Test conditions
Note
Input capacitance
C in - - 6 pF
Vin =0V
1
Input / output capacitance
C I/O - - 8 pF VI/O =0V
Note 1. This parameter is sampled and not 100% tested.
2. Ambient temperature range depends on R/I-version. Please see table on page 1.
1
AC Characteristics
Test Conditions (Vcc = 4.5V ~ 5.5V, Ta = 0 ~ +70°C / -40 ~ +85°C*1)
Input pulse levels: VIL = 0.6V, VIH = 2.4V
Input rise and fall time: 5ns
Input and output timing reference level: 1.5V
Output load: See figures (Including scope and jig)
1.5V
RL = 500 ohm
DQ
CL = 30 pF
( -5SI, -5SR)
CL = 100 pF ( -7SI, -7SR)
Note 1. Ambient temperature range depends on R/I-version. Please see table on page 1.
R10DS0070EJ0100 Rev.1.00
2011.04.13
Page 6 of 13

6 Page









R1LP5256ESP-7SR pdf, datenblatt
R1LP5256E Series
Low Vcc Data Retention Characteristics
Parameter
VCC for data retention
Symbol Min. Typ. Max. Unit
Test conditions*2
VDR
2.0
-
5.5
V
Vin 0V
CS# Vcc-0.2V
- 1*1 2 μA ~+25°C
Data retention current
- - 3 μA ~+40°C Vcc=3.0V, Vin 0V,
ICCDR
CS# Vcc-0.2V
- - 8 μA ~+70°C
- - 10 μA ~+85°C
Chip deselect to data retention time
Operation recovery time
tCDR
tR
0
5
-
-
-
-
ns
ms
See retention waveform.
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS# controls address buffer, WE# buffer, OE# buffer and Din buffer. If CS# controls data retention mode, Vin
levels (address, WE#, OE#, DQ) can be in the high impedance state.
R10DS0070EJ0100 Rev.1.00
2011.04.13
Page 12 of 13

12 Page





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