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A32100DX Schematic ( PDF Datasheet ) - Actel

Teilenummer A32100DX
Beschreibung Integrator Series FPGAs
Hersteller Actel
Logo Actel Logo 




Gesamt 30 Seiten
A32100DX Datasheet, Funktion
Integrator Series FPGAs:
1200XL and 3200DX Families
Discontinued – v3.0
Features
High Capacity
• 2,500 to 30,000 Logic Gates
• Up to 3Kbits Configurable Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Up to 250 User-Programmable I/O Pins
High Performance
• 225 MHz Performance
• 5 ns Dual-Port SRAM Access
• 100 MHz FIFOs
• 7.5 ns 35-Bit Address Decode
Ease-of-Integration
• Synthesis-Friendly Architecture Supports ASIC Design
Methodologies.
• 95–100% Device Utilization using Automatic
Place-and-Route Tools.
• Deterministic, User-Controllable Timing Via Timing
Driven Software Tools with Up To 100% Pin Fixing.
• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing.
General Description
Actel’s Integrator Series FPGAs are the first programmable
logic devices optimized for high-speed system logic
integration. Based on Actel’s proprietary antifuse
technology and 0.6-micron double metal CMOS process,
Integrator Series devices offer a fine-grained, register-rich
architecture with embedded dual-port SRAM and
wide-decode circuitry.
Integrator Series’ 3200DX and 1200XL families were
designed to integrate system logic which is typically
implemented in multiple CPLDs, PALs, and FPGAs. These
devices provide the features and performance required for
today’s complex, high-speed digital logic systems. The
3200DX family offers fast dual-port SRAM for implementing
FIFOs, LIFOs, and temporary data storage. The large
number of storage elements can efficiently address
applications requiring wide datapath manipulation and
transformation functions such as telecommunications,
networking, and DSP.
Integrator Series Product Profile Family
Device
Capacity
Logic Gates1
SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
SRAM Modules
(64x4 or 32x8)
Dedicated Flip-Flops
Clocks
User I/O (Maximum)
JTAG
A1225XL
2,500
N/A
231
220
N/A
N/A
231
2
83
No
1200XL
A1240XL
4,000
N/A
348
336
N/A
N/A
348
2
104
No
A1280XL
8,000
N/A
624
608
N/A
N/A
624
2
140
No
A3265DX
6,500
N/A
510
475
20
N/A
510
2
126
No
Packages
PL84
PQ100
VQ100
PG100
PL84 PQ100
PQ144
TQ176
PG132
PL84
PQ160 PQ208
TQ176
PG176 CQ172
Note: Logic gate capacity does not include SRAM bits as logic.
PL84
PQ100
PQ160
TQ176
A32100DX
3200DX
A32140DX
A32200DX
A32300DX
10,000
2,048
700
662
20
8
700
6
152
Yes
PL84
PQ160
PQ208
TQ176
CQ84
14,000
N/A
954
912
24
N/A
954
2
176
Yes
PL84
PQ160
PQ208
TQ176
CQ256
20,000
2,560
1,230
1,184
24
10
1,230
6
202
Yes
PQ208
RQ208
RQ240
CQ208
CQ256
30,000
3,072
1,888
1,833
28
12
1,888
6
250
Yes
RQ208
RQ240
CQ256
February 2001
© 2001 Actel Corporation
1






A32100DX Datasheet, Funktion
Integrator Series FPGAs: 1200XL and 3200DX Families
Logic Modules
3200DX and 1200XL devices contain three types of logic
modules: combinatorial (C-modules), sequential
(S-modules), and decode (D-modules). 1200XL devices
contain only the C-module and S-module, while the 3200DX
devices contain D-modules and dual-port SRAM modules in
addition to the S-module and C-module.
The C-module is shown in Figure 1 and implements the
following function:
Y=!S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11
where:
S0=A0*B0
S1=A1+B1
The S-module shown in Figure 2 is designed to implement
high-speed sequential functions within a single logic
module. The S-module implements the same combinatorial
logic function as the C-module while adding a sequential
element. The sequential element can be configured as
either a D-type flip-flop or a transparent latch. To increase
flexibility, the S-module register can be bypassed so that it
implements purely combinatorial logic.
A0
B0
A1
B1
S0
D00
D01
D10
D11
S1
Y
Figure 1 • C-Module Implementation
D00
D01
YD
Q OUT
D10
D11 S0
S1
CLR
D00
D01
YD
Q OUT
D10
D11 S0 GATE
S1
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
D0
D1
S
Y
DQ
GATE
CLR
OUT
Up to 7-Input Function Plus Latch
D00
D01 Y OUT
D10
D11 S0
S1
Up to 4-Input Function Plus Latch with Clear
Figure 2 • S-Module Implementation
Up to 8-Input Function (Same as C-Module)
6 Discontinued – v3.0

6 Page









A32100DX pdf, datenblatt
Integrator Series FPGAs: 1200XL and 3200DX Families
5.0V Operating Conditions
Absolute Maximum Ratings1
Fre e A ir Te m p er a t u re R an ge
Symbol Parameter
Limits
Units
VCC DC Supply Voltage
–0.5 to +7.0
V
VI2 Input Voltage
–0.5 to VCC +0.5
V
VO Output Voltage
–0.5 to VCC +0.5
V
TSTG
Storage Temperature
–65 to +150
°C
Notes:
1. Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Device should not be
operated outside the Recommended Operating Conditions.
2. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than VCC + 0.5V or less than GND – 0.5V, the internal protection
diode will be forward biased and can draw excessive current.
Recommended Operating Conditions
Parameter
Commercial Industrial
Military
Units
Temperature
Range1
0 to +70
–40 to +85 –55 to +125 °C
Power Supply
Tolerance
±5 ±10 ±10 %VCC
Note:
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
Electrical Specifications
Commercial
Commercial –F
Industrial
Military
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
VOH1
(IOH = –10 mA)
(IOH = –6 mA)
VOL1
(IOH = –4 mA)
(IOL = 10 mA)
(IOL = 6 mA)
VIL
VIH
Input Transition Time tR, tF
CIO I/O Capacitance2
Standby Current, ICC3 (typical = 1 mA)
ICC(D) Dynamic VCC Supply Current
IV Curve4
2.4
3.84
–0.3
2.0
0.5
0.33
0.8
VCC + 0.3
500
10
2.0
2.4
3.84
3.7 3.7
0.5
0.33
0.40
–0.3 0.8 –0.3 0.8 –0.3
2.0 VCC + 0.3 2.0 VCC + 0.3 2.0
500 500
10 10
20 10
See the “Power Dissipation” section on page 14.
Can be converted from IBIS model on the web.
0.40
0.8
VCC + 0.3
500
10
20
Notes:
1. Only one output tested at a time. VCC = min.
2. Includes worst-case 176 CPGA package capacitance. VOUT = 0 V, f = 1 MHz.
3. All outputs unloaded. All inputs = VCC or GND, typical ICC = 1 mA. ICC limit includes IPP and ISV during normal operation.
4. The IBIS model can be found at www.actel.com/support/support/support_ibis.html.
Units
V
V
V
V
V
V
V
ns
pF
mA
12 Discontinued – v3.0

12 Page





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