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Teilenummer | WPCT501 |
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Beschreibung | Trusted Platform Module (TPM) | |
Hersteller | Nuvoton | |
Logo | ||
Gesamt 21 Seiten March 2011
Revision 1.40
WPCT301/NPCT501 Trusted Platform Module (TPM) Version
1.2 with I2C Interface
General Description
The Nuvoton WPCT301/NPCT501 family of single-chip
Trusted Platform Modules (TPM) is a third-generation Nu-
voton SafeKeeper device that implements the TCG ver-
sion 1.2 specification for PC-Client TPM with the addition of
a serial data interface.
The WPCT301/NPCT501 is designed to reduce system
power-up time and Trusted OS loading time. It provides a
complete platform security solution for a wide range of com-
puter systems.
Features
General
■ Complete, single-chip TPM solution
— No external parts required
■ Compatible with the Trusted Computing Group (TCG)
TPM 1.2 Main
■ Host Interface
— TPM 1.2 Interface (TIS) emulation
— Dedicated Interrupt signal
■ Secure General-Purpose I/O (GPIO)
— Up to three GPIO pins
— I/O pins individually configured as input or output
— Configurable internal pull-up resistors
— TCG 1.2-defined interface
— Dedicated Physical Presence (PP) pin with config-
urable pull-up or pull-down resistor
■ Tick Counter
Bus Interface
■ I2C Bus Interface
— I2C Slave
— Up to 400 KHz clock operation (NPCT501)
Clocking and Supply
■ On-Chip Clock Generator
■ Power Supply
— 3.3V supply operation
— Separate pins for main (VDD) and standby (VSB)
power supplies
— Low standby power consumption
Package
■ 28-pin Thin Shrink Small Outline Package (TSSOP28)
System Block Diagram
Host
© 2011 Nuvoton Technology Corporation
Physical
Presence
I2C Bus
WPCT301/
NPCT501
GPIO
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1.0 Signal/Pin Connection and Description (Continued)
1.3.5 Reserved
Signal
NC
Reserved
Pin(s)
3, 10-14, 17, 20, 22-23, 26-27
21, 28
Description
Not Connected. These pins must be left unconnected.
Reserved. These pins must be connected to an external 10 K
pull-down resistor.
1.4 INTERNAL PULL-UP AND PULL-DOWN RESISTORS
The signals listed in Table 2 have internal pull-up (PU) and/or pull-down (PD) resistors. The internal resistors are optional for
those signals indicated as “Programmable”
Table 2. WPCT301/NPCT501 Internal Pull-Up and Pull-Down Resistors
Signal
Type
Pin(s) Power Well
WPCT301 NPCT501
Comments
SINT/GPIO4
15 VDD
PU66
PU110 GPIO4 Programmable1
GPIO3-2
9, 6 VDD
PU66
PU110 Programmable
PP
7
VDD
PU66/PD50 PU110/PD110 Programmable2
TEST
8 VDD
PD50
PD110 Strap
SADD
9 VDD
PU66
PU110 Strap
SDAT
1 VDD
PU66
PU110
1. Controlled by TPM. Default at reset: GPIO4 disabled.
2. Controlled by TPM. Default at reset: pull-down enabled.
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6
Revision 1.40
6 Page 4.0 Device Specifications (Continued)
4.2 DC CHARACTERISTICS OF PINS BY I/O BUFFER TYPES
The tables in this section summarize the DC characteristics of all device pins described in Chapter 1.2 on page 4. The char-
acteristics describe the general I/O buffer types defined in Table 1 on page 4.
4.2.1 Input, TTL Compatible, with Schmitt Trigger
Symbol: INTS
Symbol
Parameter
Conditions
Min Max Unit
VIH Input High Voltage
2 VSUP1+0.5 V
VIL Input Low Voltage
0.3 0.8 V
VH Input Hysteresis
300 mV
IILK2 Input Leakage Current
VSUP = 3.0V - 3.6V and 0 < VIN < VSUP
VSUP = 3.0V - 3.6V and VSUP < VIN
10 A
10 A
1. VSUP is VDD or VSB according to the power well of the input.
2. Input leakage current includes the output leakage of the bidirectional buffers with TRI-STATE outputs. For addi-
tional conditions, see Section 4.2.5 on page 13.
4.2.2 Input, Reset Pin
Symbol: INRST
Symbol
Parameter
Conditions
Min Max Unit
VIH Input High Voltage
0.5 VDD VDD+0.5
V
VIL Input Low Voltage
0.3
0.3 VDD
V
IILK1 Input Leakage Current
VDD = 3.0V - 3.6V and 0 < VIN < VDD
VDD = 3.0V-3.6V and VDD<VIN< VDD+0.5V
10 A
10 A
1. Input leakage current includes the output leakage of the bidirectional buffers with TRI-STATE outputs. For addi-
tional conditions, see Section 4.2.5 on page 13.
4.2.3 Output, TTL/CMOS Compatible, Push-Pull Buffer
Symbol: Op/n
Output, TTL/CMOS Compatible, rail-to-rail push-pull buffer that is capable of sourcing p mA and sinking n mA.
Symbol
Parameter
Conditions
Min Max Unit
VOH Output High Voltage
IOH = p mA
IOH = 50 A
2.4
VSUP1 0.2
V
V
VOL Output Low Voltage
IOL = n mA
IOL = 50 A
0.4 V
0.2 V
IOLK2 Output Leakage Current
VSUP = 3.0V - 3.6V and 0 < VIN < VSUP
VSUP = 3.0V - 3.6V and VSUP < VIN < VSUP+0.5V
10 A
10 A
1. VSUP is VDD or VSB according to the power well of the input.
2. Output leakage current includes the input leakage of the bidirectional buffers with TRI-STATE outputs. For
additional conditions, see Section 4.2.5 on page 13.
www.nuvoton.com
12
Revision 1.40
12 Page | ||
Seiten | Gesamt 21 Seiten | |
PDF Download | [ WPCT501 Schematic.PDF ] |
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