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EN5394QI Schematic ( PDF Datasheet ) - Altera

Teilenummer EN5394QI
Beschreibung 9A PowerSoC Voltage Mode Synchronous Buck PWM DC-DC Converter
Hersteller Altera
Logo Altera Logo 




Gesamt 19 Seiten
EN5394QI Datasheet, Funktion
Enpirion® Power Datasheet
EN5394QI 9A PowerSoC
Voltage Mode Synchronous
Buck PWM DC-DC Converter
With Integrated Inductor
Description
Typical Application Circuit
The EN5394QI is a Power Supply on a Chip
(PwrSoC) DC to DC converter with integrated
inductor, PWM controller, MOSFETS, and
compensation providing the smallest possible
solution size in a 68 pin QFN module. The
switching frequency can be synchronized to an
external clock or other EN5394QIs with the
added capability of phasing multiple EN5394QIs
as desired. Other features include precision
ENABLE threshold, pre-bias monotonic start-up,
margining, and parallel operation.
EN5394QI is specifically designed to meet the
precise voltage and fast transient requirements
of present and future high-performance
applications such as set-top boxes/HD DVRs,
LAN/SAN adapter cards, audio/video equipment,
optical networking, multi-function printers, test
and measurement, embedded computing,
storage, and servers. Advanced circuit
techniques, ultra high switching frequency, and
very advanced, high-density, integrated circuit
and proprietary inductor technology deliver high-
quality, ultra compact, non-isolated DC-DC
conversion. Operating this converter requires
very few external components.
The Altera Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity
by offering greatly simplified board design, layout
and manufacturing requirements.
All Altera Enpirion products are RoHS compliant
and lead-free manufacturing environment
compatible.
VIN
47µF
15nF
PVIN VOUT
AVIN
ENABLE
PGND VFB
SS
OCP_ADJ
PGND
AGND
VOUT
2x47µF
Figure 1: Typical Application Schematic
Features
Integrated Inductor, MOSFETS, Controller in
a 8 x 11 x 1.85mm package
Wide input voltage range of 2.375V to 6.6V.
> 30W continuous output power.
High efficiency, up to 93%.
Output voltage margining
Monotonic output voltage ramp during start-
up with pre-biased loads.
Precision Enable pin for accurate sequencing
of power converters and Power OK signal.
Programmable soft-start time.
Soft Shutdown.
4 MHz operating frequency with ability to
synchronize to an external system clock or
other EN5394’s.
Programmable phase delays between
synchronized units to allow reduction of
input ripple.
Master/slave configuration for paralleling
multiple EN5394’s for greater power output.
Under Voltage Lockout, Over-current, Short
Circuit, and Thermal Protection
RoHS compliant, MSL level 3, 260C reflow.
03738
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October 11, 2013
www.altera.com/enpirion
Rev E






EN5394QI Datasheet, Funktion
Phase Delay between
S_IN and S_OUT1
Phase Delay between
S_IN and S_OUT1
Phase Delay Accuracy1
Pre-Bias Level
Non-Monotonicity
POK Lower Threshold as
a percent of VOUT3
POK Upper Threshold as
a percent of VOUT3
POK Falling Edge
Deglitch Delay4
POK Output Low Voltage
POK Output High Voltage
Ternary Pin Logic Low5
Ternary Pin Logic High5
Ternary Pin Input Current
(see Figure 5)5
Binary Input Logic Low
Threshold6
Binary Input Logic High
Threshold6
ΦDEL
ΦDEL
VPB
VPB_NM
POKLT
POKUT
VPOKL
VPOKH
VT-Low
VT-High
ITERN
VB-Low
VB-High
EN5394QI
Phase delay programmable via
resistor connected from S_Delay 20
150 ns
to AGND.
Delay By-Pass Mode
(MAR1 floating, MAR2 high)
10 ns
-20 20 %
Allowable Pre-Bias as a fraction
of programmed output voltage
20
85 %
(subject to a minimum of 300mV)
Allowable non monotonicity
50 mV
VOUT rising
VOUT falling
92
90
%
VOUT rising
VOUT falling
120
115
%
60 µs
With 4mA current sink into POK
2.375V ≤ VIN ≤ 6.6V
Tie pin to GND
Pull up to VIN through an external
resistor REXT – see Figure 5.
VIN = 2.375V, REXT = 3.32k
VIN = 3.3V, REXT = 15k
VIN = 5.0V, REXT = 24.9k
VIN = 6.6V, REXT = 49.9k
0
see Input
Current
below
50
70
100
85
0.4
VIN
V
V
V
µA
0.8
1.8
NOTES:
1. Parameter guaranteed by design.
2. Maximum output current may need to be de-rated, based on operating condition, to meet TJ requirements.
3. POK threshold when VOUT is rising is nominally 92%. This threshold is 90% when VOUT is falling. After crossing the
90% level, there is a 256 clock cycle (~50us) delay before POK is de-asserted. The 90%, 92%, 115%, and 120%
levels are nominal values. Expect these thresholds to vary by ±3%.
4. On the falling edge of VOUT below 90% of programmed value, POK response is delayed for the duration of the
deglitch delay time. Any VOUT glitch shorter than the deglitch time is ignored.
5. M/S, MAR1, and MAR2 are ternary. Ternary pins have three logic levels: high, float, and low. These pins are only
meant to be strapped to VIN through an external resistor, strapped to GND, or left floating. Their state cannot be
changed while the device is on.
6. Binary input pins are EN_PB and OCP_ADJ.
03738
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October 11, 2013
www.altera.com/enpirion
Rev E

6 Page









EN5394QI pdf, datenblatt
of the EN5394QI input power supply.
POK is an open drain output. It requires an
external pull up. Multiple EN5394QI’s POK pins
may be connected to a single pull up. The open
drain NFET is designed to sink up to 4mA. The
pull-up resistor value should be chosen
accordingly for when POK is logic low.
Input Under-Voltage Lock-Out (UVLO)
When the input voltage is below a required
voltage level (VUVLO) for normal operation, the
converter switching is inhibited. The lock-out
threshold has hysteresis to prevent chatter.
UVLO is implemented to ensure that operation
does not begin before there is adequate voltage
to properly bias all internal circuitry.
Over-Current Protection (OCP)
The current limit and short-circuit protection is
achieved by sensing the current flowing through
a sense P-FET. When the sensed current
exceeds the current limit, both NFET and PFET
switches are turned off. If the over-current
condition is removed, the over-current protection
circuit will re-enable the PWM operation. If the
over-current condition persists, the circuit will
continue to protect the device.
The OCP trip point is nominally set to 150% of
maximum rated load. In the event the OCP circuit
trips, the device enters a hiccup mode. The
device is disabled for ~10msec and restarted
with a normal soft-start. This cycle can continue
indefinitely as long as the over current condition
persists. During soft-start at power up or fault
EN5394QI
recovery, the hiccup mode is disabled and the
device has cycle-by-cycle current limiting. Tie
OCP_ADJ pin to GND for proper OCP operation.
Thermal Overload Protection
Thermal shutdown will disable operation when
the Junction temperature exceeds approximately
150ºC. Once the junction temperature drops by
approximately 20ºC, the converter will re-start
with a normal soft-start.
Compensation
The EN5394 uses of a type III compensation
network. Most of this network is integrated.
However a phase lead capacitor is required in
parallel with upper resistor of the external divider
network (see Figure 4). This network results in a
wide loop bandwidth and excellent load transient
performance. It is optimized for approximately
100μF of output filter capacitance at the voltage
sensing point. Additional decoupling capacitance
may be placed beyond the voltage sensing point
outside the control loop. Voltage-mode operation
provides high noise immunity at light load.
Further, voltage-mode control provides superior
impedance matching to ICs processed in sub
90nm technologies.
In exceptional cases modifications to the
compensation may be required. The EN5394QI
provides the capability to modify the control loop
response to allow for customization for specific
applications. For more information, contact Altera
Power Applications support.
Application Information
Output Voltage Programming
The EN5394 output voltage is determined by the
voltage presented at the VFB pin. This voltage is
set by way of a resistor divider between VOUT and
AGND with the midpoint going to VFB. A phase
lead capacitor CA is also required for stabilizing
the loop. Figure 4 shows the required
components and the equations to calculate their
values. Please note the equations below are
written to optimize the control loop as a function
of input voltage.
VOUT
RA
RB
RA = 30,000 ×Vin (value in )
CA
CA
=
5.6 ×106
RA
(CA /R A in F/)
Round CA down to closest
VFB standard value lower than
calculated value.
RB
= VFB × RA
(VOUT VFB )

VFB is 0.6V
nominal

Figure 4: Output voltage resistor divider and phase-
03738
12
October 11, 2013
www.altera.com/enpirion
Rev E

12 Page





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