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Teilenummer | ADP3207D |
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Beschreibung | 7-Bit Programmable Multi-Phase Mobile CPU Synchronous Buck Controller | |
Hersteller | ON Semiconductor | |
Logo | ||
Gesamt 30 Seiten ADP3207D
7-Bit Programmable,
Multi-Phase Mobile, CPU
Synchronous Buck
Controller
The ADP3207D is a high efficiency, multi−phase, synchronous,
buck−switching regulator controller optimized for converting
notebook battery voltage into the core supply voltage required by high
performance Intel processors. The part uses an internal 7−bit
Digital−to−Analog Converter (DAC) to read Voltage Identification
(VID) code directly from the processor that sets the output voltage.
The phase relationship of the output signals can be programmed to
provide 1−, 2−, or 3−phase operation, allowing for the construction of
up to three interleaved buck−switching stages.
The ADP3207D uses a multi−mode architecture to drive the
logic−level PWM outputs at a programmable switching frequency that
can be optimized depending on the output current requirement. The
part switches between multi−phase and single−phase operation to
maximize its effectiveness under all load conditions. In addition, the
ADP3207D includes a programmable slope function to adjust the
output voltage as a function of the load current. As a result, it is always
best positioned for a system transient.
The chip also provides accurate and reliable short−circuit
protection, adjustable current limiting, and a delayed power−good
output that accommodates On−the−Fly (OTF) output voltage changes
requested by the CPU.
The ADP3207D is specified over the extended commercial
temperature range of −10°C to 100°C and is available in a 40−lead
LFCSP.
The ADP3207DF has a soft−start time one tenth of ADP3207D.
There are no other differences between the ADP3207D and
ADP3207DF.
http://onsemi.com
LFCSP40
CASE 932AC
MARKING DIAGRAM
ADP3207D
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YYWW = Date Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 31 of this data sheet.
Features
• 1−, 2−, or 3−Phase Operation at Up to 750 kHz per Phase
• $7 mV Worst−Case Differential Sensing Error
Overtemperature
• Input Voltage Range of 3.3 V to 22 V
• Interleaved PWM Outputs for Driving External High
Power MOSFET Drivers
• Enhanced PWM FlexModet for Excellent Load
Transient Performance
• Automatic Power−Saving Modes Maximize Efficiency
During Light Load and Deeper Sleep Operation
• Soft Transient Control Reduces Inrush Current and
Audio Noise
• Active Current Balancing Between Output Phases
• Independent Current Limit and Load Line Setting
Inputs for Additional Design Flexibility
• Built−In, Power−Good Masking Supports VID OTF
• 7−Bit Digitally Programmable 0.3 V to 1.5 V Output
• Overload and Short−Circuit Protection Latchoff Delay
• Built−In, Clock Enable Output Delays CPU Clock Until
CPU Supply Voltage Stabilizes
• Current Monitor Output Signals the Total Output Power
of the Buck Converter
• This is a Pb−Free Device
Applications
• Notebook Power Supplies for Next Generation
Intel® Processors
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 0
1
Publication Order Number:
ADP3207D/D
ADP3207D
ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = GND, EN = VCC, VVID = 0.50 V to 1.5000 V, PSI = 1.05 V,
DPRSLP = GND, DPRSTP= 1.05 V, LLSET = CSREF, TA = −10°C to 100°C, unless otherwise noted (Note 1). RREF = 80 kW.
Current entering a pin (sunk by the device) has a positive sign.
Parameter
Symbol
Conditions
Min Typ
VOLTAGE MONITORING AND PROTECTION − Power Good
CSREF Reverse Voltage
Threshold
VRVCSREF
Relative to FBRTN, Latchoff mode:
CSREF Falling
CSREF Rising
−350
−300
−70
PWRGD Low Voltage
PWRGD High, Leakage
Current
VPWRGD
IPWRGD
IPWRGD(SINK) = 4 mA
VPWRDG = 5.0 V
85
PWRGD Startup Delay
TSSPWRGD
Measured from CLKEN neg edge to PWRGD
Pos Edge
8.0
PWRGD Latchoff Delay
TLOFFPWRGD
Measured from Out−off−Good−Window event
to Latchoff (switching stops)
8.0
PWRGD Propagation Delay
TPDPWRGD
Measured from Out−off−Good−Window event
to PWRGD neg edge
200
Crowbar Latchoff Delay
(Note 2)
TLOFFCB
Measured from Crowbar event to Latchoff
(switching stops)
200
PWRGD Masking Time
Triggered by any VID change or OCP event
100
CSREF Soft−Stop
Resistance
EN = L or Latchoff condition
70
CURRENT CONTROL − Current Sense Amplifier (CSAMP)
CSSUM, CSREF Common−Mode Range
(Note 2)
Voltage range of interest
0
CSSUM, CSREF Offset
Voltage
VOSCSA
CSSUM Bias Current
CSREF Bias Current
CSCOMP Voltage Range (Note 2)
IBCSSUM
IBCSREF
CSREF − CSSUM, TA = −10°C to 85°C
TA = 25°C
Operating Range
−1.7
−0.5
−50
−50
0.05
CSCOMP Current
CSCOMP Slew Rate
ICSCOMPsource
ICSCOMPsink
CSCOMP = 2.0 V
CSSUM forced 200 mV below CSREF
CSSUM forced 200 mV above CSREF
CCSCOMP = 10 pF, Open Loop Configuration
CSSUM forced 200 mV below CSREF
CSSUM forced 200 mV above CSREF
−750
1.0
10
−10
Gain Bandwidth (Note 2)
GBWCSA
CURRENT MONITORING AND PROTECTION
Non−inverting unit gain configuration
RFB = 1 kW
20
Current Reference
IREF Voltage
Current Limiter (OCP)
Current Limit Threshold
VREF
VLIMTH
RREF = 80 kW to set IREF = 20 mA
Measured from CSCOMP to CSREF,
RLIM = 4.5 kW,
2−ph configuration, PSI = H
2−ph configuration, PSI = L
Measured from CSCOMP to CSREF,
RLIM = 4.5 kW,
3−ph configuration, PSI = H
3−ph configuration, PSI = L
1−ph configuration
1.55 1.6
−70 −90
−30 −45
−70 −90
−15 −30
−70 −90
Current Limit Latchoff Delay
Measured from OCP event to PWRGD
deassertion
8.0
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
Max
−5.0
150
1.0
2.0
+1.7
+0.5
+50
+50
2.0
1.65
−115
−65
−115
−50
−115
Unit
mV
mV
mA
ms
ms
ns
ns
ms
W
V
mV
nA
nA
V
mA
mA
V/ms
MHz
V
mV
ms
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6
6 Page ADP3207D
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT VOLTAGE
DPRSLP
SW1
SW3
SW2
Input = 12 V
Output = 1.0 V
1 A Load
PSI = Low
Figure 18. DPRSLP Transition
OUTPUT VOLTAGE
DPRSLP
SW1
SW3
SW2
Input = 12 V
Output = 1.0 V
1 A Load
PSI = Low
Figure 19. DPRSLP Transition
OUTPUT VOLTAGE
DPRSLP
SW1
SW3
SW2
Input = 12 V
Output = 1.0 V
1 A Load
PSI = High
Figure 20. DPRSLP Transition
OUTPUT VOLTAGE
DPRSLP
SW1
SW3
SW2
Input = 12 V
Output = 1.0 V
1 A Load
PSI = High
Figure 21. DPRSLP Transition
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12
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ ADP3207D Schematic.PDF ] |
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