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PDF ADuC7061 Data sheet ( Hoja de datos )
| Número de pieza | ADuC7061 | |
| Descripción | Low Power Precision Analog Microcontroller | |
| Fabricantes | Analog Devices | |
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Data Sheet
Low Power, Precision Analog Microcontroller,
Dual Sigma-Delta ADCs, Flash/EE, ARM7TDMI
ADuC7060/ADuC7061
FEATURES
Analog input/output
Dual (24-bit) ADCs
Single-ended and differential inputs
Programmable ADC output rate (4 Hz to 8 kHz)
Programmable digital filters
Built-in system calibration
Low power operation mode
Primary (24-bit) ADC channel
2 differential pairs or 4 single-ended channels
PGA (1 to 512) input stage
Selectable input range: ±2.34 mV to ±1.2 V
30 nV rms noise
Auxiliary (24-bit) ADC: 4 differential pairs or 7 single-
ended channels
On-chip precision reference (±10 ppm/°C)
Programmable sensor excitation current sources
200 μA to 2 mA current source range
Single 14-bit voltage output DAC
Microcontroller
ARM7TDMI core, 16-/32-bit RISC architecture
JTAG port supports code download and debug
Multiple clocking options
Memory
32 kB (16 kB × 16) Flash/EE memory, including 2 kB kernel
4 kB (1 kB × 32) SRAM
Tools
In-circuit download, JTAG based debug
Low cost, QuickStart™ development system
Communications interfaces
SPI interface (5 Mbps)
4-byte receive and transmit FIFOs
UART serial I/O and I2C (master/slave)
On-chip peripherals
4× general-purpose (capture) timers including
Wake-up timer
Watchdog timer
Vectored interrupt controller for FIQ and IRQ
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
16-bit, 6-channel PWM
General-purpose inputs/outputs
Up to 14 GPIO pins that are fully 3.3 V compliant
Power
AVDD/DVDD specified for 2.5 V (±5%)
Active mode: 2.74 mA (@ 640 kHz, ADC0 active)
10 mA (@ 10.24 MHz, both ADCs active)
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Packages and temperature range
Fully specified for −40°C to +125°C operation
32-lead LFCSP (5 mm × 5 mm)
48-lead LFCSP and LQFP
Derivatives
32-lead LFCSP (ADuC7061)
48-lead LQFP and 48-lead LFCSP (ADuC7060)
APPLICATIONS
Industrial automation and process control
Intelligent, precision sensing systems, 4 mA to 20 mA
loop-based smart sensors
GENERAL DESCRIPTION
The ADuC706x series are fully integrated, 8 kSPS, 24-bit data acqui-
sition systems incorporating high performance multichannel
sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), 16-bit/
32-bit ARM7TDMI® MCU, and Flash/EE memory on a single chip.
The ADCs consist of a primary ADC with two differential pairs or
four single-ended channels and an auxiliary ADC with up to seven
channels. The ADCs operate in single-ended or differential input
mode. A single-channel buffered voltage output DAC is available
on chip. The DAC output range is programmable to one of four
voltage ranges.
The devices operate from an on-chip oscillator and a PLL gene-
rating an internal high frequency clock up to 10.24 MHz. The
microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC
machine offering up to 10 MIPS peak performance; 4 kB of SRAM
and 32 kB of nonvolatile Flash/EE memory are provided on chip.
The ARM7TDMI core views all memory and registers as a single
linear array.
The ADuC706x contains four timers. Timer1 is a wake-up timer
with the ability to bring the part out of power saving mode. Timer2
is configurable as a watchdog timer. A 16-bit PWM with six output
channels is also provided. The ADuC706x contains an advanced
interrupt controller. The vectored interrupt controller (VIC) allows
every interrupt to be assigned a priority level. It also supports
nested interrupts to a maximum level of eight per IRQ and FIQ.
When IRQ and FIQ interrupt sources are combined, a total of 16
nested interrupt levels is supported. On-chip factory firmware
supports in-circuit serial download via the UART serial interface
ports and nonintrusive emulation via the JTAG interface. The parts
operate from 2.375 V to 2.625 V over an industrial temperature
range of −40°C to +125°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009–2012 Analog Devices, Inc. All rights reserved.
1 page  
Data Sheet
ADuC7060/ADuC7061
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 2.5 V ± 5%, VREF+ = 1.2 V, VREF− = GND, fCORE = 10.24 MHz driven from an external 32.768 kHz watch crystal or on-chip oscillator, all
specifications TA = −40°C to +125°C, unless otherwise noted. Output noise specifications can be found in Table 36 (primary ADC) and
Table 38 (ADC auxiliary channel).
Table 1. ADuC706x Specifications
Parameter
Test Conditions/Comments
ADC SPECIFICATIONS
For all ADC specifications,
assume normal operating mode
unless specifically stated
otherwise
Conversion Rate1
Chop off, ADC normal operating
mode
Chop on, ADC normal operating
mode
Chop on, ADC low power mode
Main Channel
No Missing Codes1
Chop off (fADC ≤ 1 kHz)
Chop on (fADC ≤ 666 Hz)
Integral Nonlinearity1, 2
Gain = 4
Offset Error3, 4
Chop off, offset error is in the
order of the noise for the pro-
grammed gain and update rate
following calibration
Offset Error1, 3, 4
Chop on
Offset Error Drift vs.
Temperature5
Chop off (with gain ≤ 64)
Chop on (with gain ≤ 64)
Full-Scale Error1, 6, 7, 8
Normal mode
Full-Scale Error6,8
Low power mode
Gain Drift vs. Temperature9
PGA Gain Mismatch Error
Power Supply Rejection1
Chop on, ADC = 1 V (gain = 1)
Chop on, ADC = 7.8 mV (gain =
128)
Chop off, ADC = 1 V (gain = 1)
Auxiliary Channel
No Missing Codes1
Chop off (fADC ≤ 1 kHz)
Chop on (fADC ≤ 666 Hz)
Integral Nonlinearity1
Offset Error4
Chop off
Offset Error1, 4
Chop on
Offset Error Drift vs.
Temperature5
Chop off
Chop on
Full-Scale Error1,6,7,8
Normal mode
Full-Scale Error1,6,8
Low power mode
Gain Drift vs. Temperature9
Power Supply Rejection1
Chop on, ADC = 1 V
Chop off, ADC = 1 V
Min
50
4
1
24
24
−27
−2.7
−1
−2
84.7
56
24
24
−120
−1.5
−1
−2
55
53
Typ Max Unit
8000
2600
650
±15
±8 +27
±0.5 +2.7
650/PGA_GAIN
10
±0.5 +1
±1.0 +2
5
±0.1
65
113
65
±15
±30 +100
±0.5 +3.2
200
10
±0.5 +1
±1.0 +2
3
65
65
Hz
Hz
Hz
Bits
Bits
ppm of FSR
μV
μV
nV/°C
nV/°C
mV
mV
ppm/°C
%
dB
dB
dB
Bits
Bits
ppm of FSR
μV
μV
nV/°C
nV/°C
mV
mV
ppm/°C
dB
dB
Rev. D | Page 5 of 108
5 Page 
Data Sheet
SPI Timing
Table 3. SPI Master Mode Timing (Phase Mode = 1)
Parameter
Description
tSL SCLOCK low pulse width
tSH SCLOCK high pulse width
tDAV Data output valid after SCLOCK edge
tDSU Data input setup time before SCLOCK edge1
tDHD Data input hold time after SCLOCK edge1
tDF Data output fall time
tDR Data output rise time
tSR SCLOCK rise time
tSF SCLOCK fall time
1 tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL.
ADuC7060/ADuC7061
Min
1 × tUCLK
2 × tUCLK
Typ
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
Max
25
30 40
30 40
30 40
30 40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLOCK
(POLARITY = 0)
SCLOCK
(POLARITY = 1)
MOSI
tSH
tSL
tDAV
tDF
MSB
tSR
tDR
BITS 6 TO 1
tSF
LSB
MISO
MSB IN
BITS 6 TO 1
tDSU
tDHD
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
LSB IN
Table 4. SPI Master Mode Timing (Phase Mode = 0)
Parameter
Description
tSL SCLOCK low pulse width
tSH SCLOCK high pulse width
tDAV Data output valid after SCLOCK edge
tDOSU Data output setup before SCLOCK edge
tDSU Data input setup time before SCLOCK edge1
tDHD Data input hold time after SCLOCK edge1
tDF Data output fall time
tDR Data output rise time
tSR SCLOCK rise time
tSF SCLOCK fall time
1 tUCLK = 97.6 ns. It corresponds to the 10.24 MHz internal clock from the PLL.
Min
1 × tUCLK
2 × tUCLK
Typ
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
Max
25
90
30 40
30 40
30 40
30 40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. D | Page 11 of 108
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADuC7061.PDF ] | |
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