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WM8988 Schematic ( PDF Datasheet ) - Wolfson Microelectronics

Teilenummer WM8988
Beschreibung Stereo CODEC
Hersteller Wolfson Microelectronics
Logo Wolfson Microelectronics Logo 




Gesamt 30 Seiten
WM8988 Datasheet, Funktion
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WM8988
Stereo CODEC for Portable Audio Applications
DESCRIPTION
The WM8988 is a low power, high quality stereo CODEC
designed for portable digital audio applications.
The device integrates complete interfaces to 2 stereo
headphone or line out ports. External component
requirements are drastically reduced as no separate
headphone amplifiers are required. Advanced on-chip digital
signal processing performs graphic equaliser, 3-D sound
enhancement and automatic level control for the
microphone or line input.
The WM8988 can operate as a master or a slave, with
various master clock frequencies including 12 or 24MHz for
USB devices, or standard 256fs rates like 12.288MHz and
24.576MHz. Different audio sample rates such as 96kHz,
48kHz, 44.1kHz are generated directly from the master
clock without the need for an external PLL.
The WM8988 operates at supply voltages down to 1.8V,
although the digital core can operate at voltages down to
1.42V to save power, and the maximum for all supplies is
3.6 Volts. Different sections of the chip can also be powered
down under software control.
The WM8988 is supplied in a very small and thin 4x4mm
COL package, ideal for use in hand-held and portable
systems.
FEATURES
DAC SNR 100dB (‘A’ weighted), THD –90dB at 48kHz, 3.3V
ADC SNR 93dB (‘A’ weighted), THD -81dB at 48kHz, 3.3V
Programmable ALC / Noise Gate
2x On-chip Headphone Drivers
- >40mW output power on 16/ 3.3V
- THD –80dB at 20mW, SNR 90dB with 16load
Digital Graphic Equaliser
Low Power
- 7mW stereo playback (1.8V / 1.5V supplies)
- 14mW record and playback (1.8V / 1.5V supplies)
Low Supply Voltages
- Analogue 1.8V to 3.6V
- Digital core: 1.42V to 3.6V
- Digital I/O: 1.8V to 3.6V
256fs / 384fs or USB master clock rates: 12MHz, 24MHz
Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48,
88.2, 96kHz generated internally from master clock
4x4mm COL package
APPLICATIONS
Portable Multimedia players
Multimedia handsets
Handheld gaming
BLOCK DIAGRAM
DGND
DCVDD
DBVDD
HPGND HPVDD
LINPUT1
LINPUT2
RINPUT2
RINPUT1
DIFF.
INPUT
L1-R1 OR
L2-R2
M LMIXSEL
U
X
DC MEASUREMENT
M PGA
U + MIC
X BOOST
LINSEL
ANALOGUE
MONO MIX
RINSEL
M PGA
U + MIC
X BOOST
DC MEASUREMENT
M
U
X RMIXSEL
50K 50K
W
WM8988
ADC
ADC
DIGITAL
FILTERS
VOLUME
DIGITAL
MONO MIX
DIGITAL
FILTERS
GRAPHIC
EQUALISER
BASS
BOOST
DAC
DAC
LEFT
LD2LO MIXER
LI2LO
RD2LO
RI2LO
RIGHT
LD2RO MIXER
LI2RO
RD2RO
RI2RO
AUDIO
INTERFACE
CLOCK
CIRCUITRY
CONTROL
INTERFACE
LOUT1
(headphone / line output
LOUT1VOL
HPCOM
ROUT1
ROUT1VOL (headphone / line output
LOUT2
LOUT2VOL (headphone / line output
LCOM
ROUT2
(headphone / line output
ROUT2VOL
WOLFSON MICROELECTRONICS plc
Production Data, October 2013, Rev 4.1
Copyright 2013 Wolfson Microelectronics plc






WM8988 Datasheet, Funktion
WM8988
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
DCVDD = 1.5V, DBVDD = 2.4V, AVDD = HPVDD =2.4V , TA = +25oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB, 24-bit audio
data unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
Analogue Inputs (LINPUT1, RINPUT1, LINPUT2, RINPUT2) to ADC out
Full Scale Input Signal Level
(for ADC 0dB Input at 0dB Gain)
VINFS
AVDD = 3.3V
AVDD = 2.4V
AVDD = 1.8V
Input Resistance
RIN L/RINPUT1 to ADC,
PGA gain = 0dB
L/RINPUT1 to ADC,
PGA gain = +30dB
L/RINPUT2 to ADC
PGA gain = 0dB
Input Capacitance
L/RINPUT2 to ADC
PGA gain = 30dB
Signal to Noise Ratio
(A-weighted)
SNR
AVDD = 3.3V
AVDD = 2.4V
Total Harmonic Distortion
THD
AVDD = 1.8V
-1dBFs input,
AVDD = 3.3V
-1dBFS input,
AVDD = 2.4V
Total Harmonic Distortion +
Noise
THD+N
-1dBFs input,
AVDD = 1.8V
-1dBFs input,
AVDD = 3.3V
-1dBFS input,
AVDD = 2.4V
-1dBFs input,
AVDD = 1.8V
ADC Channel Separation
1kHz signal
Channel Matching
10kHz signal
1kHz signal
Analogue Outputs (LOUT1/2, ROUT1/2)
0dB Full scale output voltage
VOUTFS
AVDD = 3.3V
AVDD = 2.4V
Mute attenuation
Channel Separation
AVDD = 1.8V
1kHz, full scale signal
1kHz signal
PGA Gain range
10kHz signal
guaranteed monotonic
PGA step size
MIN
0.95
0.690
0.480
16
1.5
16
1.5
80
80
78
-0.5
0.95
0.690
0.507
+6
0.25
TYP
1.0
0.727
0.545
22
2.8
22
2.8
10
93
88
87
-81
-80
-76
-75
-70
-70
85
85
0.2
1.0
0.727
0.545
90
85
85
1
MAX
1.05
0.763
0.610
-68
-68
-65
-65
-65
-60
+0.5
1.05
0.763
0.583
-67
1.25
UNIT
Vrms
k
pF
dB
dB
dB
dB
dB
Vrms
dB
dB
dB
dB
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PD, Rev 4.1, October 2013
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6 Page









WM8988 pdf, datenblatt
WM8988
Production Data
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Bit Clock Timing Information
BCLK rise time (10pF load)
BCLK fall time (10pF load)
BCLK duty cycle (normal mode, BCLK = MCLK/n)
BCLK duty cycle (USB mode, BCLK = MCLK)
tBCLKR
tBCLKF
tBCLKDS
tBCLKDS
50:50
TMCLKDS
3
3
ns
ns
Audio Data Input Timing Information
DACLRC propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
tDL
tDDA
tDST
tDHT
10
10
10 ns
10 ns
ns
ns
AUDIO INTERFACE TIMING – SLAVE MODE
BCLK
LRC
DACDAT
ADCDAT
t
BCH
t
BCL
t
BCY
t
DS
t
DD
t
LRH
t
DH
t
LRSU
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
DACLRC set-up time to BCLK rising edge
DACLRC hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
ADCDAT propagation delay from BCLK falling edge
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
tDD
50
20
20
10
10
10
ns
ns
ns
ns
ns
ns
10 ns
Note:
BCLK period should always be greater than or equal to MCLK period.
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PD, Rev 4.1, October 2013
12

12 Page





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