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EMP8966 Schematic ( PDF Datasheet ) - Elite Semiconductor

Teilenummer EMP8966
Beschreibung 600mA Micropower CMOS Linear Regulator
Hersteller Elite Semiconductor
Logo Elite Semiconductor Logo 




Gesamt 20 Seiten
EMP8966 Datasheet, Funktion
ESMT/EMP
EMP8966
Fast Ultra High-PSRR, Low-Noise, Low-Dropout,
600mA Micropower CMOS Linear Regulator
General Description
The EMP8966 low-dropout (LDO) CMOS linear regulators,
feature ultra-high power supply rejection ratio (75dB at
1kHz), low output voltage noise (30µV), low dropout
voltage (270mV), low quiescent current (110µA), and fast
transient response. It guarantees delivery of 600mA output
current, and supports adjustable (1.2V to 5.0V) output
voltage versions.
The EMP8966 is ideal for battery-powered applications by
virtue of its low quiescent current consumption and its 1nA
shutdown mode of logical operation. The regulator
provides fast turn-on and start-up time by using dedicated
circuitry to pre-charge an optional external bypass
capacitor. This bypass capacitor is used to reduce the
output voltage noise without adversely affecting the load
transient response. The high power supply rejection ratio of
the EMP8966 holds well for low input voltages typically
encountered in battery- operated systems. The regulator is
stable with small ceramic capacitive loads (2.2µF typical).
Additional features include regulation fault detection,
bandgap voltage reference, constant current limiting and
thermal overload protection. Available in miniature 5-pin
SOT-89-5 package options, SOT-23-5,SOT-23-6 package
options are also offered to provide additional flexibility
for different applications.
EMP products is RoHS compliant.
Features
„ Miniature SOT-23-5, SOT-23-6and SOT-89-5 packages
„ 600mA guaranteed output current
„ 75dB typical PSRR at 1kHz
„ 30µV RMS output voltage noise (10Hz to 100kHz)
„ 270mV typical dropout at 600mA
„ 110µA typical quiescent current
„ 1nA typical shutdown mode
„ Fast line and load transient response
„ 80µs typical fast turn-on time
„ 2.5V to 5.5V input range
„ Stable with small ceramic output capacitors
„ Over temperature and over current protection
„ ±2% output voltage tolerance
Applications
„ Wireless handsets
„ PCMCIA cards
„ DSP core power
„ Hand-held instruments
„ Battery-powered systems
„ Portable information appliances
Elite Semiconductor Memory Technology Inc. /Elite MicroPower Inc.
Publication Date : May 2009
Revision : 1.1
1/20






EMP8966 Datasheet, Funktion
ESMT/EMP
Absolute Maximum Ratings (Notes 1, 2)
EMP8966
VIN, VOUT, V SHDN , VSET, VCC, V FAULT
Power Dissipation
Storage Temperature Range
Junction Temperature (TJ)
Lead Temperature (10 sec.)
ESD Rating
Human Body Model (Note 5)
MM
-0.3V to 6.0V
(Note 3)
-65°C to160°C
150°C
260°C
2kV
200V
Thermal Resistance (θJA) (Note 3)
SOT-23-5
SOT-23-6
SOT-89-5
250°C/W
250°C/W
100°C/W
Operating Ratings (Note 1), (Note 2)
Temperature Range
-40°C to 85°C
Supply Voltage
2.5V to 5.5V
Electrical Characteristics
Unless otherwise specified, all limits guaranteed for VIN = VOUT +1V (Note 6), V SHDN = VIN, CIN = COUT = 2.2µF, CCC = 33nF, TJ =
25°C. Boldface limits apply for the operating temperature extremes: -40°C and 85°C.
Symbol
Parameter
Conditions
Typ
Min
Max
Units
(Note 7)
VIN Input Voltage
2.5 5.5 V
ΔVOTL
100µA IOUT 300mA
VOUT (NOM) +0.5V VIN 5.5V
Output Voltage Tolerance (Note 6)
ADJ = VOUT for the Adjust
-2
-3
+2
% of
VOUT (NOM)
+3
Versions
VOUT
Output Adjust Range
1.20 5.0 V
IOUT Maximum Output Current Average DC Current Rating 600
mA
Output Current Limit
(SOT-23-5, SOT-23-6)
ILIMIT
Output Current Limit
(SOT-89-5)
600 950
630 950
mA
mA
Supply Current
IQ
IOUT = 0mA
IOUT = 600mA
Shutdown Supply Current VOUT = 0V, SHDN = GND
110
255 µA
0.001
1
Dropout Voltage
VDO
(Note 4), (Note 6)
IOUT = 50mA
IOUT = 300mA
IOUT = 600mA
22
130 mV
270
IOUT = 1mA, (VOUT + 0.5V) VIN
ΔVOUT
Line Regulation
5.5V
(Note 7)
-0.1 0.02
0.1 %/V
Load Regulation
100µA IOUT 600mA
0.001
%/mA
en Output Voltage Noise IOUT = 10mA, 10Hz f 100kHz
30
µVRMS
V SHDN
SHDN Input Threshold
VIH, (VOUT + 0.5V) VIN 5.5V
(Note 6)
VIL, (VOUT + 0.5V) VIN 5.5V
(Note 6)
1.2
V
0.4
I SHDN
SHDN Input Bias Current SHDN = GND or VIN
0.1 100 nA
IADJ ADJ Input Leakage
ADJ=1.3V,
0.1 3 nA
Elite Semiconductor Memory Technology Inc. /Elite MicroPower Inc.
Publication Date : May 2009
Revision : 1.1
6/20

6 Page









EMP8966 pdf, datenblatt
ESMT/EMP
EMP8966
Application Information
General Description
Referring to Figure 2 as shown in the Functional Block
Diagram section, the EMP8966 adopts the classical
regulator topology in which negative feedback control is
used to perform the desired voltage regulating function.
The negative feedback is formed by using feedback
resistors (R1, R2) to sample the output voltage for the
non-inverting input of the error amplifier, whose inverting
input is set to the bandgap reference voltage. By virtue of
its high open-loop gain, the error amplifier operates to
ensure that the sampled output feedback voltage at its
non-inverting input is virtually equal to the preset bandgap
reference voltage. These feedback resistors can be either
internal or external to the EMP8966, depending on whether
a preset or an adjustable output voltage version is being
used.
The error amplifier compares the voltage difference at its
inputs and produces an appropriate driving voltage to the
P-channel MOS pass transistor to control the amount of
current reaching the output. If there are changes in the
output voltage due to load changes, the feedback
resistors register such changes to the non-inverting input of
the error amplifier. The error amplifier then adjusts its driving
voltage to maintain virtual short between its two input
nodes under all loading conditions. In a nutshell, the
regulation of the output voltage is achieved as a direct
result of the error amplifier keeping its input voltages equal.
This negative feedback control topology is further
augmented by the shutdown, the fault detection, and the
temperature and current protection circuitry.
Output Voltage Control
The EMP8966 allows direct user control of the output
voltage in accordance with the amount of negative
feedback present. To see the explicit relationship between
the output voltage and the negative feedback, it is
convenient to conceptualize the EMP8966 as an ideal
non-inverting operational amplifier with a fixed DC
reference voltage VREF at its non-inverting input. Such a
conceptual representation
of the EMP8966 in closed-loop configuration is shown in
Figure 3. This ideal op amp features an ultra-high input
resistance such that its inverting input voltage is virtually
fixed at VREF. The output voltage is therefore given by:
V
OUT
=
V
REF
⎢⎣⎡RR21
+
1
This equation can be rewritten in the following form to
facilitate the determination of the resistor values for a
chosen output voltage:
R1
=
R
2
⎢⎣
VOUT
1.19V
1⎥⎦
Set R2 equal to 100kΩ to optimize for overall accuracy,
power supply rejection, noise, and power consumption.
VREVF REF
VVININ
+
R2 R2
-
R1
R1
VOVUTOUT
Figure 3. Simplified Regulator Topology
Output Capacitor
The EMP8966 is specially designed for use with ceramic
output capacitors of as low as 2.2µF to take advantage of
the savings in cost and space as well as the superior
filtering of high frequency noise. Capacitors of higher value
or other types may be used, but it is important to make sure
its equivalent series resistance (ESR) be restricted to less
than 0.5Ω. The use of larger capacitors with smaller ESR
values is desirable for applications
involving large and fast input or output transients, as well as
for situations where the application systems are not
physically located immediately adjacent to the
Elite Semiconductor Memory Technology Inc. /Elite MicroPower Inc.
Publication Date : May 2009
Revision : 1.1
12/20

12 Page





SeitenGesamt 20 Seiten
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