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PDF EMP8021-33VI05NRR Data sheet ( Hoja de datos )
| Número de pieza | EMP8021-33VI05NRR | |
| Descripción | 600mA CMOS Linear Regulator | |
| Fabricantes | Elite Semiconductor | |
| Logotipo |  |
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ESMT/EMP
Preliminary
EMP8021
600mA CMOS Linear Regulator
General Description
The EMP8021 low-dropout (LDO) CMOS linear regulators
feature low output voltage noise (63µV), low quiescent
current (50µA), and fast transient response. It
guarantees delivery of 600mA output current, and
supports preset output voltages ranging from 0.8V to
4.75V with 0.05V increment.
Applications
g Wireless handsets
g PCMCIA cards
g DSP core power
g Hand-held instruments
g Battery-powered systems
g Portable information appliances
The EMP8021 is ideal for battery-powered applications
by virtue of its low quiescent current consumption and
its 1nA shutdown mode of logical operation. The
regulator provides fast turn-on and start-up time by
using dedicated circuitry to pre-charge an optional
external bypass capacitor. This bypass capacitor is used
to reduce the output voltage noise without adversely
affecting the load transient response. The regulator is
stable with small ceramic capacitive loads (2.2µF
typical).
Additional features include bandgap voltage
reference, constant current limiting and thermal
overload protection. The EMP8021 is available in
miniature 5-pin SOT-23-5 package.
Features
g Miniature SOT-23-5 packages
g 600mA guaranteed output current
g 63µV RMS output voltage noise (10Hz to 100kHz)
(Vout=3.3V, Cbypass=10nF)
g 580mV typical dropout at 600mA(Vout=3.3V)
g 270mV typical dropout at 300mA(Vout=3.3V)
g 50µA typical quiescent current
g 1nA typical shutdown mode
g Fast line and load transient response
g 140µs typical fast turn-on time (Vout=3.3V,
Cbypass=10nF)
g 2.2V to 5.5V input range
g Stable with small ceramic output capacitors
g Over temperature and over current protection
g ±2% output voltage tolerance
Typical Application
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Apr. 2011
Revision: 0.3
1/13
1 page  
ESMT/EMP
Preliminary
VEN
EN Input Threshold
IEN EN Input Bias Current
Thermal Shutdown
Temperature
TSD
Thermal Shutdown
Hysteresis
TON Start-Up Time
IOUT=10mA,10Hz ≤ f ≤ 100kHz
VOUT = 3.3V,Cbypass = float
VIH, (VOUT + 1V) ≤ VIN ≤ 5.5V
(Note 8)
VIL, (VOUT + 1V) ≤ VIN ≤ 5.5V
(Note 8)
EN = GND or VIN
1.2
COUT = 10µF, VOUT at 90% of
Final Value
EMP8021
205
V
0.4
0.1 100 nA
167
℃
30
140 µs
Note 1: Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not
apply when operating the device outside of its rated operating conditions.
Note 2: All voltages are with respect to the potential at the ground pin.
Note 3: θJA is measured in the natural convection at TA=25℃ on a high effective thermal conductivity test board
(2 layers , 2S0P ) of JEDEC 51-7 thermal measurement standard.
Note 4: θJC represents the resistance to the heat flows the chip to package top case.
Note 5: Maximum Power dissipation for the device is calculated using the following equations:
PD
=
TJ(MAX)
θJA
-
TA
Where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the
junction-to-ambient thermal resistance. E.g. for the SOT-23-5 packageθJA = 135°C/W, TJ (MAX) = 150°C and
using TA = 25°C, the maximum power dissipation is found to be 925mW. The derating factor (-1/θJA) =
-7.4mW/°C, thus below 25°C the power dissipation figure can be increased by 7.4mW per degree, and
similarity decreased by this factor for temperatures above 25°C.
Note 6: Typical Values represent the most likely parametric norm.
Note 7: Human body model: 1.5kΩ in series with 100pF.
Note 8: Condition does not apply to input voltages below 2.2V since this is the minimum input operating voltage.
Note 9: Dropout voltage is measured by reducing VIN until VOUT drops 100mV from its nominal value. Dropout voltage
does not apply to the regulator versions with VOUT less than 1.8V.
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Apr. 2011
Revision: 0.3
5/13
5 Page 
ESMT/EMP
Package Outline Drawing
SC-70-5
Preliminary
EMP8021
θ2
SYMBPLS
A
A1
A2
B
C
D
E
E1
E
e1
L
L1
θ°
θ2°
MIN.
0.8
0
0.8
0.15
0.08
1.85
1.8
1.10
0.26
0
4
NOM. MAX.
－ 1.10
－ 0.10
0.90
－
1.00
0.30
－ 0.22
2.00 2.15
2.10 2.40
1.25 1.40
0.65 BSC
1.30 BSC
0.36 0.46
0.42 REF
48
－ 12
UNIT: MM
θo
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Apr. 2011
Revision: 0.3
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet EMP8021-33VI05NRR.PDF ] | |
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