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EMP8020-33VF05NRR Schematic ( PDF Datasheet ) - Elite Semiconductor

Teilenummer EMP8020-33VF05NRR
Beschreibung 300mA CMOS Linear Regulator
Hersteller Elite Semiconductor
Logo Elite Semiconductor Logo 




Gesamt 15 Seiten
EMP8020-33VF05NRR Datasheet, Funktion
ESMT/EMP
Preliminary
EMP8020
Fast Ultra High-PSRR, Low-Noise, Low-Dropout,
300mA CMOS Linear Regulator
General Description
The EMP8020 low-dropout (LDO) CMOS linear regulator
features an ultra-high power supply rejection ratio (78dB
at 1kHz), low output voltage noise (48µV), low dropout
voltage, low quiescent current (50µA), and fast
transient response. It guarantees a delivery of 300mA
output current, and supports preset output voltages
ranging from 0.8V to 4.75V with 0.05V increments.
The EMP8020 is ideal for battery-powered applications
because of its low quiescent current consumption and
its 1nA shutdown mode. The regulator provides fast
turn-on and start-up time by using dedicated circuitry to
pre-charge an optional external bypass capacitor. This
bypass capacitor is used to reduce the output voltage
noise without adversely affecting the load transient
response. The high power supply rejection ratio of the
EMP8020 holds well for low input voltages typically
encountered in battery operated systems. The regulator
is stable with small ceramic capacitive loads (2.2µF
typical).
Additional features include bandgap voltage
reference, constant current limiting, and thermal
overload protection. Both of Miniature 5-pin
SC-70-5/SOT-23-5 and 4-pin SC-82-4 package options
are offered to provide flexibility for different
applications.
Applications
„ Wireless handsets
„ PCMCIA cards
„ DSP core power
„ Hand-held instruments
„ Battery-powered systems
„ Portable information appliances
Features
„ Miniature SC-70-5,SOT-23-5 and SC-82-4
packages
„ 300mA guaranteed output current
„ PSRR 78dB typical at 1kHz
70dB typical at 10kHz
„ 48µV RMS output voltage noise (10Hz to 100kHz)
(Vout=2.8V, Cbypass=10nF)
„ 305mV typical dropout at 300mA (Vout=2.8V)
„ 50µA typical quiescent current
„ 1nA typical shutdown mode
„ Fast line and load transient response
„ 140µs typical fast turn-on time (Vout=2.8V,
Cbypass=10nF)
„ 2.2V to 5.5V input range
„ Stable with small ceramic output capacitors
„ Over-temperature and over-current protection
„ ±2% output voltage tolerance
Typical Application
EMP8020
15
VIN VIN VOUT
1uF
3
ON/OFF
EN
* Use 2.2uF for VOUT < 1.2V
CC (NC)
GND
2
4
10nF
VOUT
1uF *
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Mar. 2011
Revision: 0.7
1/15






EMP8020-33VF05NRR Datasheet, Funktion
ESMT/EMP
Preliminary
EMP8020
ΔVOUT
Line Regulation
Load Regulation
en Output Voltage Noise
VEN
EN Input Threshold
IOUT = 1mA, (VOUT + 0.5V) VIN
5.5V
(Note 7)
-0.1
100µA IOUT 300mA
IOUT=10mA,10Hz f 100kHz
Cbypass = 10nF
IOUT=10mA,10Hz f 100kHz
Cbypass = float
VIH, (VOUT + 0.5V) VIN 5.5V
(Note 7)
VIL, (VOUT + 0.5V) VIN 5.5V
(Note 7)
1.2
0.02
0.001
45
145
0.1 %/V
%/mA
µVRMS
V
0.4
IEN EN Input Bias Current
EN = GND or VIN
0.1 100 nA
Thermal Shutdown
Temperature
TSD
Thermal Shutdown
Hysteresis
167
30
COUT = 10µF, VOUT at 90% of
TON Start-Up Time
140 µs
Final Value
Note 1: Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not
apply when operating the device outside of its rated operating conditions.
Note 2: All voltages are with respect to the potential at the ground pin.
Note 3: θJA is measured in the natural convection at TA=25on a high effective thermal conductivity test board
(2 layers , 2S0P ) of JEDEC 51-7 thermal measurement standard.
Note 4: Maximum Power dissipation for the device is calculated using the following equation:
PD
=
TJ(MAX)
θJA
-
TA
Where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the
junction-to-ambient thermal resistance. E.g. for the SOT-23-5 packageθJA = 250°C/W, TJ (MAX) = 150°C and
using TA = 25°C, the maximum power dissipation is found to be 500mW. The derating factor (-1/θJA) =
-4.0mW/°C, thus below 25°C the power dissipation figure can be increased by 4.0mW per degree, and
similarity decreased by this factor for temperatures above 25°C.
Note 5: Typical Values represent the most likely parametric norm.
Note 6: Human body model: 1.5kΩ in series with 100pF.
Note 7: Condition does not apply to input voltages below 2.2V since this is the minimum input operating voltage.
Note 8: Dropout voltage is measured by reducing VIN until VOUT drops 100mV from its nominal value. Dropout voltage
does not apply to the regulator versions with VOUT less than 1.8V.
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Mar. 2011
Revision: 0.7
6/15

6 Page









EMP8020-33VF05NRR pdf, datenblatt
ESMT/EMP
Package Outline Drawing
SOT-23-5
Preliminary
EMP8020
θ2
SYMBPLS
A
A1
A2
B
C
D
E
E1
E
e1
L
L1
θ°
θ
MIN.
1.05
0.05
1.00
0.30
0.08
2.80
2.60
1.50
0.30
0
6
NOM. MAX.
1.20 1.35
0.10 0.15
1.10
1.20
0.50
0.20
2.90 3.00
2.80 3.00
1.60 1.70
0.95 BSC
1.90 BSC
0.45 0.55
0.60 REF
5 10
8 10
UNIT: MM
θo
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Mar. 2011
Revision: 0.7
12/15

12 Page





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