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AD5695R Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5695R
Beschreibung Quad 16-/14-/12-Bit nanoDAC+
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD5695R Datasheet, Funktion
Data Sheet
Quad 16-/14-/12-Bit nanoDAC+
with 2 ppm/°C Reference, I2C Interface
AD5696R/AD5695R/AD5694R
FEATURES
High relative accuracy (INL): ±2 LSB maximum @ 16 bits
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
Low glitch: 0.5 nV-sec
400 kHz I2C-compatible serial interface
Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Optical transceivers
Base-station power amplifiers
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5696R/AD5695R/AD5694R family, are low power,
quad, 16-/14-/12-bit buffered voltage output DACs. The devices
include a 2.5 V, 2 ppm/°C internal reference (enabled by
default) and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). All devices operate from a single
2.7 V to 5.5 V supply, are guaranteed monotonic by design, and
exhibit less than 0.1% FSR gain error and 1.5 mV offset error
performance. The devices are available in a 3 mm × 3 mm
LFCSP and a TSSOP package.
The AD5696R/AD5695R/AD5694R also incorporate a power-
on reset circuit and a RSTSEL pin that ensures that the DAC
outputs power up to zero scale or midscale and remain there
until a valid write takes place. Each part contains a per-channel
power-down feature that reduces the current consumption of
the device to 4 µA at 3 V while in power-down mode.
The AD5696R/AD5695R/AD5694R use a versatile 2-wire serial
interface that operates at clock rates up to 400 kHz, and
includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic.
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
VLOGIC
SCL
SDA
A1
A0
AD5696R/AD5695R/AD5694R
2.5V
REFERENCE
INPUT
REGISTER
DAC
STRING
REGISTER DAC A
INPUT
REGISTER
DAC
STRING
REGISTER DAC B
INPUT
REGISTER
DAC
STRING
REGISTER DAC C
INPUT
REGISTER
DAC
STRING
REGISTER DAC D
POWER-ON
RESET
GAIN =
×1/×2
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
POWER-
DOWN
LOGIC
VOUTD
LDAC RESET
RSTSEL
Figure 1.
GAIN
Table 1. Quad nanoDAC+ Devices
Interface Reference 16-Bit
SPI Internal AD5686R
External AD5686
I2C Internal AD5696R
External AD5696
14-Bit
AD5685R
AD5695R
12-Bit
AD5684R
AD5684
AD5694R
AD5694
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5696R (16-bit): ±2 LSB maximum
AD5695R (14-bit): ±1 LSB maximum
AD5694R (12-bit): ±1 LSB maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD5695R Datasheet, Funktion
AD5696R/AD5695R/AD5694R
Data Sheet
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1
Table 4.
Parameter2
t1
t2
t3
t4
t5
t63
t7
t8
t9
t10
t11
t12
t13
tSP5
CB4
Min
2.5
0.6
1.3
0.6
100
0
0.6
0.6
1.3
0
20 + 0.1CB4
20
400
0
Max
0.9
300
300
50
400
Unit
μs
μs
μs
μs
ns
μs
μs
μs
μs
ns
ns
ns
ns
ns
pF
Conditions/Comments
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
tSU,STA, setup time for repeated start
tSU,STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tF, fall time of SDA and SCL when transmitting/ receiving
LDAC pulse width
SCL rising edge to LDAC rising edge
Pulse width of suppressed spike
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization; not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s
falling edge.
4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
5 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.
SDA
SCL
START
CONDITION
t9
t3
t4
LDAC1
t10
t6
LDAC2
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
REPEATED START
CONDITION
t11 t4
t2
t5
t1
t7
t13
t12
Figure 2. 2-Wire Serial Interface Timing Diagram
STOP
CONDITION
t8 t12
Rev. B | Page 6 of 32

6 Page









AD5695R pdf, datenblatt
AD5696R/AD5695R/AD5694R
1.4
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
1.2
1.0
0.8
0.6
0.4 ZERO-CODE ERROR
0.2
OFFSET ERROR
0
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 23. Zero-Code Error and Offset Error vs. Temperature
0.10
0.08
0.06
0.04
0.02
0
–0.02
GAIN ERROR
FULL-SCALE ERROR
–0.04
–0.06
–0.08
–0.10
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY VOLTAGE (V)
Figure 24. Gain Error and Full-Scale Error vs. Supply
1.5
1.0
0.5
0
–0.5
ZERO-CODE ERROR
OFFSET ERROR
–1.0
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–1.5
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY VOLTAGE (V)
Figure 25. Zero-Code Error and Offset Error vs. Supply
Data Sheet
0.10
VDD = 5V
0.09 TA = 25°C
INTERNAL REFERENCE = 2.5V
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
Figure 26. TUE vs. Temperature
100 120
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–0.10
2.7 3.2 3.7 4.2
4.7
SUPPLY VOLTAGE (V)
Figure 27. TUE vs. Supply, Gain = 1
5.2
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
VDD = 5V
TA = 25°C
INTERNAL REFERENCE = 2.5V
–0.10
0 10000 20000 30000
40000
50000
CODE
Figure 28. TUE vs. Code
60000 65535
Rev. B | Page 12 of 32

12 Page





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