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ADSP-21160M Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-21160M
Beschreibung Digital Signal Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-21160M Datasheet, Funktion
SUMMARY
High performance 32-bit DSP—applications in audio, medi-
cal, military, graphics, imaging, and communication
Super Harvard architecture—4 independent buses for dual
data fetch, instruction fetch, and nonintrusive, zero-over-
head I/O
Backward compatible—assembly source level compatible
with code for ADSP-2106x DSPs
Single-instruction, multiple-data (SIMD) computational
architecture—two 32-bit IEEE floating-point computation
units, each with a multiplier, ALU, shifter, and register file
Integrated peripherals—integrated I/O processor, 4M bits
on-chip dual-ported SRAM, glueless multiprocessing fea-
tures, and ports (serial, link, external bus, and JTAG)
SHARC
Digital Signal Processor
ADSP-21160M/ADSP-21160N
FEATURES
100 MHz (10 ns) core instruction rate (ADSP-21160N)
Single-cycle instruction execution, including SIMD opera-
tions in both computational units
Dual data address generators (DAGs) with modulo and bit-
reverse addressing
Zero-overhead looping and single-cycle loop setup, provid-
ing efficient program sequencing
IEEE 1149.1 JTAG standard Test Access Port and on-chip
emulation
400-ball 27 mm × 27 mm PBGA package
Available in lead-free (RoHS compliant) package
200 million fixed-point MACs sustained performance
(ADSP-21160N)
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 x 48-BIT
DAG1
DAG2
8 x 4 x 32 8 x 4 x 32
PROGRAM
SEQUENCER
PM ADDRESS BUS
32
DM ADDRESS BUS
32
BUS
CONNECT
(PX)
PM DATA BUS 16/32/40/48/64
DM DATA BUS
32/40/64
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
ADDR
DATA
DATA ADDR
ADDR
DATA
DATA ADDR
IOD IOA
64 18
JTAG
TEST AND
EMULATION
6
EXTERNAL
PORT
ADDR BUS
MUX
32
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
64
HOST PORT
MULT
DATA
REGISTER
FILE
(PEX)
16 x 40-BIT
BARREL
SHIFTER
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16 x 40-BIT
MULT
ALU
IOP
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS AND
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
LINK PORTS
(6)
I/O PROCESSOR
4
6
6
60
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADSP-21160M Datasheet, Funktion
ADSP-21160M/ADSP-21160N
ADSP-21160X #6
ADSP-21160X #5
ADSP-21160X #4
ADSP-21160X #3
CLKIN
RESET
ADDR31–0
DATA63–0
RPBA
3
ID2–0
011
CONTROL
PA
BR1–2, BR4–6
BR3
5
ADSP-21160X #2
CLKIN ADDR31–0
RESET DATA63–0
RPBA
3
ID2–0
010
CONTROL
PA
BR1, BR3–6
BR2
5
ADSP-21160X #1
CLKIN
RESET
ADDR31–0
DATA63–0
RPBA
RDx
3
ID2–0
WRx
ACK
MS3–0
001
BUS
PRIORITY
RESET
CLOCK
BMS
PAGE
SBTS
CS
HBR
HBG
REDY
PA
BR2–6
BR1
5
ADDR
DATA
OE
WE
ACK
CS
CS
ADDR
DATA
GLOBAL MEMORY
AND
PERIPHERALS
(OPTIONAL)
BOOT EPROM (OPTIONAL)
ADDR
DATA
HOST PROCESSOR
INTERFACE (OPTIONAL)
Figure 3. Shared Memory Multiprocessing System
Rev. D | Page 6 of 58 | September 2015

6 Page









ADSP-21160M pdf, datenblatt
ADSP-21160M/ADSP-21160N
Table 3. Pin Function Descriptions (Continued)
Pin
PAGE
BRST
ACK
SBTS
IRQ2–0
FLAG3–0
TIMEXP
HBR
HBG
CS
REDY
DMAR1
DMAR2
Type
O/T
I/O/T
I/O/S
I/S
I/A
I/O/A
O
I/A
I/O
I/A
O (O/D)
I/A
I/A
Function
DRAM Page Boundary. The processor asserts this pin to an external DRAM controller, to signal that
an external DRAM page boundary has been crossed. DRAM page size must be defined in the
processor’s memory control register (WAIT). DRAM can only be implemented in external memory
Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system, PAGE
is output by the bus master. A keeper latch on the DSP’s PAGE pin maintains the output at the level
it was last driven (only enabled on the processor with ID2–0 = 00x).
Sequential Burst Access. BRST is asserted by ADSP-21160x or a host to indicate that data associated
with consecutive addresses is being read or written. A slave device samples the initial address and
increments an internal address counter after each transfer. The incremented address is not
pipelined on the bus. If the burst access is a read from the host to the processor, the
processor automatically increments the address as long as BRST is asserted. BRST is asserted after
the initial access of a burst transfer. It is asserted for every cycle after that, except for the last data
request cycle (denoted by RDx or WRx asserted and BRST negated). A keeper latch on the DSP’s
BRST pin maintains the input at the level it was last driven (only enabled on the processor with
ID2–0 = 00x).
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off
completion of an external memory access. The ADSP-21160x deasserts ACK as an output to add
wait states to a synchronous access of its internal memory, by a synchronous host or another DSP
in a multiprocessor configuration. ACK has a 2 kinternal pull-up resistor that is enabled on the
processor with ID2–0 = 00x.
Suspend Bus and Three-State. External devices can assert SBTS (low) to place the external bus
address, data, selects, and strobes in a high-impedance state for the following cycle. If the
ADSP-21160x attempts to access external memory while SBTS is asserted, the processor will halt
and the memory access will not be completed until SBTS is deasserted. SBTS should only be used
to recover from host processor and/or ADSP-21160x deadlock or used with a DRAM controller.
Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be either edge-
triggered or level-sensitive.
Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be tested
as a condition. As an output, it can be used to signal external peripherals.
Timer Expired. Asserted for four processor core clock (CCLK) cycles when the timer is enabled and
TCOUNT decrements to zero.
Host Bus Request. Must be asserted by a host processor to request control of the
ADSP-21160x DSP’s external bus. When HBR is asserted in a multiprocessing system, the processor
that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the processor places
the address, data, select, and strobe lines in a high-impedance state. HBR has priority over all
processor bus requests (BR6–1) in a multiprocessing system.
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take
control of the external bus. HBG is asserted (held low) by the ADSP-21160x until HBR is released. In
a multiprocessing system, HBG is output by the processor bus master and is monitored by all others.
After HBR is asserted, and before HBG is given, HBG will float for 1 tCLK
(1 CLKIN cycle). To avoid erroneous grants, HBG should be pulled up with a 20 kto 50 kexternal
resistor.
Chip Select. Asserted by host processor to select the ADSP-21160x, for asynchronous transfer
protocol.
Host Bus Acknowledge. The ADSP-21160x deasserts REDY (low) to add wait states to an
asynchronous host access when CS and HBR inputs are asserted.
DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services.
DMAR1 has a 20 kinternal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.
DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services.
DMAR2 has a 20 kinternal pull-up resistor that is enabled on the ADSP-21160x with ID2–0 = 00x.
Rev. D | Page 12 of 58 | September 2015

12 Page





SeitenGesamt 30 Seiten
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