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AD7452 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7452
Beschreibung 12-Bit ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 29 Seiten
AD7452 Datasheet, Funktion
FEATURES
Specified for VDD of 3 V and 5 V
Low power at max throughput rate:
3.3 mW max at 555 kSPS with 3 V supplies
7.25 mW max at 555 kSPS with 5 V supplies
Fully differential analog input
Wide input bandwidth:
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®/QSPI™/MICROWIRE™/DSP compatible
Power-down mode: 1 µA max
8-lead SOT-23 package
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
Motor control
GENERAL DESCRIPTION
The AD74521 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
fully differential analog input. This part operates from a single
3 V or 5 V power supply and features throughput rates up to
555 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies up to 3.5 MHz. The reference voltage is applied
externally to the VREF pin and can be varied from 100 mV to
3.5 V depending on the power supply and what suits the
application. The value of the reference voltage determines the
common-mode voltage range of the part. With this truly
differential input structure and variable reference input, the
user can select a variety of input ranges and bias points.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled on
the falling edge of CS, and the conversion is also initiated at this
point.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Differential Input, 555 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7452
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
VIN–
VREF
12-BIT
T/H SUCCESSIVE
APPROXIMATION
ADC
AD7452
CONTROL LOGIC
SCLK
SDATA
CS
GND
Figure 1.
The SAR architecture of this part ensures that there are no
pipeline delays.
The AD7452 uses advanced design techniques to achieve very
low power dissipation.
PRODUCT HIGHLIGHTS
1. Operation with Either 3 V or 5 V Power Supplies.
2. High Throughput with Low Power Consumption. With a
3 V supply, the AD7452 offers 3.3 mW max power
consumption for 555 kSPS throughput.
3. Fully Differential Analog Input.
4. Flexible Power/Serial Clock Speed Management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. This part also
features a shutdown mode to maximize power efficiency at
lower throughput rates.
5. Variable Voltage Reference Input.
6. No Pipeline Delay.
7. Accurate Control of the Sampling Instant via a CS Input
and Once-Off Conversion Control.
8. ENOB > 8 Bits Typically with 100 mV Reference.
1 Protected by U.S. Patent Number 6,681,332.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






AD7452 Datasheet, Funktion
AD7452
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a 1.6 V voltage
level. See Figure 2 and the Serial Interface section.
VDD = 2.7 V to 3.6 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V;
VCM1 = VREF; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
fSCLK 2
tCONVERT
tQUIET
t1
t2
t33
t43
t5
t6
t7
t8 4
tPOWER-UP5
Limit at TMIN, TMAX
10
10
16 × tSCLK
1.6
60
10
10
20
40
0.4 tSCLK
0.4 tSCLK
10
10
35
1
Unit
kHz min
MHz max
µs max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs max
Description
tSCLK = 1/fSCLK
Minimum quiet time between the end of a serial read and the next falling edge of CS
Minimum CS pulse width
CS falling edge to SCLK falling edge setup time
Delay from CS falling edge until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SCLK edge to data valid hold time
SCLK falling edge to SDATA three-state enabled
SCLK falling edge to SDATA three-state enabled
Power-up time from full power-down
CS
SCLK
t2
t3
SDATA
t1
123
t4
00 0 0
4 LEADING ZEROS
t5
4
tCONVERT
5
t7
DB11 DB10
B
13 14
t6
15
t8
DB2
DB1
DB0
16
tQUIET
THREE-STATE
Figure 2. Serial Interface Timing Diagram
1 Common-mode voltage.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, or 0.4 V or 2.0 V for VDD = 3 V.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish
time of the part and is independent of the bus loading.
5 See Power-Up Time section.
Rev. B | Page 5 of 28

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AD7452 pdf, datenblatt
3.0
2.5
2.0
1.5
1.0
POSITIVE DNL
0.5
0
–0.5
NEGATIVE DNL
–1.0
0
0.5 1.0 1.5 2.0 2.5 3.0
VREF (V)
Figure 11. Change in DNL vs. VREF for VDD = 5 V
3.5
2.5
2.0
1.5
1.0
POSITIVE DNL
0.5
0
–0.5
NEGATIVE DNL
–1.0
0 0.5 1.0 1.5 2.0 2.2
VREF (V)
Figure 12. Change in DNL vs. VREF for VDD = 3 V
2.5
5
4
3
2
1 POSITIVE INL
0
–1 NEGATIVE INL
–2
–3
–4
–5
0 0.5 1.0 1.5 2.0 2.5 3.0
VREF (V)
Figure 13. Change in INL vs. VREF for VDD = 5 V
3.5
AD7452
2.0
1.5
1.0
POSITIVE INL
0.5
0
–0.5 NEGATIVE INL
–1.5
–2.0
0
0.5 1.0 1.5 2.0 2.2
VREF (V)
Figure 14. Change in INL vs. VREF for VDD = 3 V
2.5
8
7
6
VDD = 5V
5
4
3
2 VDD = 3V
1
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VREF (V)
Figure 15. Change in Zero-Code Error vs. Reference Voltage VDD = 5 V and 3 V
12.0
11.5
11.0
10.5
VDD = 3V
VDD = 5V
10.0
9.5
9.0
8.5
8.0
7.5
7.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
VREF (V)
Figure 16. Change in ENOB vs. Reference Voltage VDD = 5 V and 3 V
Rev. B | Page 11 of 28

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