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AD7441 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7441
Beschreibung 10-/12-Bit ADCs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
AD7441 Datasheet, Funktion
Pseudo Differential Input, 1 MSPS,
10-/12-Bit ADCs in an 8-Lead SOT-23
AD7441/AD7451
FEATURES
Fast throughput rate: 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Low power at maximum throughput rate:
4 mW maximum at 1 MSPS with VDD = 3 V
9.25 mW maximum at 1 MSPS with VDD = 5 V
Pseudo differential analog input
Wide input bandwidth:
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Power-down mode: 1 μA maximum
8-lead SOT-23 and MSOP packages
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
GENERAL DESCRIPTION
The AD7441/AD74511 are, respectively, 10-/12-bit high speed,
low power, single-supply, successive approximation (SAR),
analog-to-digital converters (ADCs) that feature a pseudo
differential analog input. These parts operate from a single
2.7 V to 5.25 V power supply and achieve very low power
dissipation at high throughput rates of up to 1 MSPS.
The AD7441/AD7451 contain a low noise, wide bandwidth,
differential track-and-hold (T/H) amplifier that handles input
frequencies up to 3.5 MHz. The reference voltage for these
devices is applied externally to the VREF pin and can range from
100 mV to VDD, depending on the power supply and what suits
the application.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled
on the falling edge of CS when the conversion is initiated.
The SAR architecture of these parts ensures that there are no
pipeline delays.
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
VIN–
VREF
12-BIT
T/H
SUCCESSIVE
APPROXIMATION
ADC
AD7441/AD7451 CONTROL LOGIC
SCLK
SDATA
CS
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. Operation with 2.7 V to 5.25 V Power Supplies.
2. High Throughput with Low Power Consumption.
With a 3 V supply, the AD7441/AD7451 offer 4 mW maxi-
mum power consumption for a 1 MSPS throughput rate.
3. Pseudo Differential Analog Input.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. These
parts also feature a shutdown mode to maximize power
efficiency at lower throughput rates.
5. Variable Voltage Reference Input.
6. No Pipeline Delays.
7. Accurate Control of Sampling Instant via CS Input and
Once-Off Conversion Control.
8. ENOB > 10 Bits Typically with 500 mV Reference.
1 Protected by U.S. Patent Number 6,681,332.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved.






AD7441 Datasheet, Funktion
AD7441/AD7451
VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted. Temperature range for
B version: −40°C to +85°C.
Table 2. AD7441
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)1
Total Harmonic Distortion (THD)1
Peak Harmonic or Spurious Noise1
Intermodulation Distortion (IMD)1
Second-Order Terms
Third-Order Terms
Aperture Delay1
Aperture Jitter1
Full-Power Bandwidth1, 2
DC ACCURACY
Resolution
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Offset Error1
Gain Error1
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
VIN+
VIN– 3
DC Leakage Current
Input Capacitance
REFERENCE INPUT
VREF Input Voltage4
DC Leakage Current
VREF Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN5
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
Test Conditions/Comments
fIN = 100 kHz
2.7 V to 3.6 V; −77 dB typical
4.75 V to 5.25 V; −79 dB typical
2.7 V to 3.6 V; −80 dB typical
4.75 V to 5.25 V; −82 dB typical
fa = 90 kHz, fb = 110 kHz
@ −3 dB
@ −0.1 dB
B Version
61
−72
−73
−72
−74
−80
−80
5
50
20
2.5
Guaranteed no missed codes to 10 bits
10
±0.5
±0.5
±1
±1
VIN+ − VIN–
VREF
VDD = 2.7 V to 3.6 V
VDD = 4.75 V to 5.25 V
When in track-and-hold
VREF
−0.1 to +0.4
−0.1 to +1.5
±1
30/10
±1% tolerance for specified performance
When in track-and-hold
2.5
±1
10/30
Typically 10 nA, VIN = 0 V or VDD
2.4
0.8
±1
10
VDD = 4.75 V to 5.25 V; ISOURCE = 200 μA
VDD = 2.7 V to 3.6 V; ISOURCE = 200 μA
ISINK = 200 μA
2.8
2.4
0.4
±1
10
Straight (natural) binary
Unit
dB min
dB max
dB max
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
V
V
V
V
μA max
pF typ
V
μA max
pF typ
V min
V max
μA max
pF max
V min
V min
V max
μA max
pF max
Rev. D | Page 5 of 24

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AD7441 pdf, datenblatt
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
0
POSITIVE DNL
NEGATIVE DNL
1234
VREF (V)
Figure 13. Change in DNL vs. VREF for VDD = 5 V
5
5
4
3
2
1
POSITIVE DNL
0
NEGATIVE DNL
–1
–2
01234
VREF (V)
Figure 14. Change in INL vs. VREF for VDD = 5 V
5
12
VDD = 3V
11
10
9
8
VDD = 5V
7
6
01234
VREF (V)
Figure 15. ENOB vs. VREF for VDD = 5 V and 3 V
5
AD7441/AD7451
0
–20
–40
–60
–80
–100
–120
–140
0
8192 POINT FFT
fSAMPLE = 1MSPS
fIN = 100kSPS
SINAD = 61.7dB
THD = –81.7dB
SFDR = –82dB
100 200 300 400
VREF (V)
Figure 16. AD7441 Dynamic Performance
500
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
256 512 768
CODE
Figure 17. Typical DNL for the AD7441
1024
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
256 512 768
CODE
Figure 18. Typical INL for the AD7441
1024
Rev. D | Page 11 of 24

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