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DS1338C-3 Schematic ( PDF Datasheet ) - Maxim Integrated

Teilenummer DS1338C-3
Beschreibung I2C RTC
Hersteller Maxim Integrated
Logo Maxim Integrated Logo 




Gesamt 16 Seiten
DS1338C-3 Datasheet, Funktion
19-6019; Rev 3/12
DS1338
I2C RTC with 56-Byte NV RAM
GENERAL DESCRIPTION
The DS1338 serial real-time clock (RTC) is a low-
power, full binary-coded decimal (BCD)
clock/calendar plus 56 bytes of NV SRAM. Address
and data are transferred serially through an I2C
interface. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year
information. The end of the month date is
automatically adjusted for months with fewer than 31
days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator. The DS1338 has a built-in power-
sense circuit that detects power failures and
automatically switches to the backup supply,
maintaining time and date operation
APPLICATIONS
Handhelds (GPS, POS Terminal)
Consumer Electronics (Set-Top Box, Digital
Recording, Network Appliance)
Office Equipment (Fax/Printer, Copier)
Medical (Glucometer, Medicine Dispenser)
Telecommunications (Router, Switcher, Server)
Other (Utility Meter, Vending Machine, Thermostat,
Modem)
TYPICAL OPERATING CIRCUIT
RPU = tr/Cb
VCC RPU
VCC
CRYSTAL
RPU
VCC
CPU
X1 X2
VCC
SCL SQW/OUT
DS1338
SDA
GND
VBAT
i
FEATURES
RTC Counts Seconds, Minutes, Hours, Date
of the Month, Month, Day of the Week, and
Year with Leap-Year Compensation Valid Up
to 2100
Available in a Surface-Mount Package with an
Integrated Crystal (DS1338C)
56-Byte Battery-Backed General-Purpose
RAM with Unlimited Writes
I2C Serial Interface
Programmable Square-Wave Output Signal
Automatic Power-Fail Detect and Switch
Circuitry
-40°C to +85°C Operating Temperature Range
Underwriters Laboratories (UL) Recognized
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE TOP MARK
DS1338Z-18+
DS1338Z-3+
DS1338Z-33+
DS1338U-18+
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
DS1338U-3+ -40°C to +85°C
DS1338U-33+
DS1338C-18#
-40°C to +85°C
-40°C to +85°C
8 SO (0.150)
8 SO (0.150)
8 SO (0.150)
8 µSOP
8 µSOP
8 µSOP
16 SO (0.300)
DS1338-18
DS1338-3
DS133833
1338
rr-18
1338
rr-3
1338
rr-33
DS1338C-18
DS1338C-3# -40°C to +85°C 16 SO (0.300) DS1338C-3
DS1338C-33# -40°C to +85°C 16 SO (0.300) DS1338C-33
rr = second line, revision level
+ Denotes a lead(Pb)-free/RoHS-compliant device.
# Denotes a RoHS-compliant device that may include lead that is
exempt under the RoHS requirements. The lead finish is JESD97
category e3, and is compatible with both lead-based and lead-free
soldering processes.
A “+” anywhere on the top mark denotes a lead-free device. A “#”
denotes a RoHS-compliant device.
Pin Configurations appear at end of data sheet.
1 of 16






DS1338C-3 Datasheet, Funktion
TYPICAL OPERATING CHARACTERISTICS
DS1338 I2C RTC with 56-Byte NV RAM
IBAT vs. VBAT
VCC=0V
RS1=RS0=1
1250
1200
1150
1100
1050
IBAT OSC2
(SQWE = 1)
1000
950
900
IBAT OSC1
(SQWE = 0)
850
800
750
700
650
600
550
1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
VBAT (V)
1000
950
900
850
800
750
700
650
600
-40
IBAT vs. Temperature
VBAT = 3.0V
SQWE=1
SQWE=0
-20 0 20 40 60
TEMPERATURE (°C)
VCC=0V
80
ICC vs. VCC
250
SCL=400kHz
225
200
175
SCL=SDA=0Hz
150
125
100
75
50
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
VCC (V)
Oscillator Frequency vs. Supply Voltage
32768.5
32768.4
32768.3
32768.2
32768.1
32768.0
1.3
1.8 2.3 2.8 3.3 3.8 4.3
Oscillator Supply Voltage (V)
4.8
6 of 16

6 Page









DS1338C-3 pdf, datenblatt
DS1338 I2C RTC with 56-Byte NV RAM
I2C SERIAL DATA BUS
The DS1338 supports the I2C protocol. A device that sends data onto the bus is defined as a transmitter and a
device receiving data is a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. The bus must be controlled by a master device, which generates
the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1338
operates as a slave on the I2C bus. Within the bus specifications, a standard mode (100kHz maximum clock rate)
and a fast mode (400kHz maximum clock rate) are defined. The DS1338 works in both modes. Connections to the
bus are made through the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 5).
Data transfer can be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines
the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable
for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is not limited and is determined by the master device. The
information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception
of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that
the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and
hold times must be taken into account. A master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data
line HIGH to enable the master to generate the STOP condition.
Figure 5. Data Transfer on I2C Serial Bus
12 of 16

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