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AD9874 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9874
Beschreibung IF Digitizing Subsystem
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9874 Datasheet, Funktion
IF Digitizing Subsystem
AD9874*
FEATURES
10 MHz to 300 MHz Input Frequency
7.2 kHz to 270 kHz Output Signal Bandwidth
8.1 dB SSB NF
0 dBm IIP3
AGC Free Range up to –34 dBm
12 dB Continuous AGC Range
16 dB Front End Attenuator
Baseband I/Q 16-Bit (or 24-Bit) Serial Digital Output
LO and Sampling Clock Synthesizers
Programmable Decimation Factor, Output Format,
AGC, and Synthesizer Settings
370 Input Impedance
2.7 V to 3.6 V Supply Voltage
Low Current Consumption: 20 mA
48-Lead LQFP Package (1.4 mm Thick)
APPLICATIONS
Multimode Narrow-Band Radio Products
Analog/Digital UHF/VHF FDMA Receivers
TETRA, APCO25, GSM/EDGE
Portable and Mobile Radio Products
Base Station Applications
SATCOM Terminals
GENERAL DESCRIPTION
The AD9874 is a general-purpose IF subsystem that digitizes a
low level 10 MHz to 300 MHz IF input with a signal bandwidth
ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9874
consists of a low noise amplifier, a mixer, a band-pass sigma-delta
analog-to-digital converter, and a decimation filter with program-
mable decimation factor. An automatic gain control (AGC) circuit
gives the AD9874 12 dB of continuous gain adjustment. Auxil-
iary blocks include both clock and LO synthesizers.
The AD9874’s high dynamic range and inherent antialiasing
provided by the band-pass sigma-delta converter allow the
AD9874 to cope with blocking signals up to 95 dB stronger
than the desired signal. This attribute can often reduce the cost of
a radio by reducing its IF filtering requirements. Also, it enables
multimode radios of varying channel bandwidths, allowing the
IF filter to be specified for the largest channel bandwidth.
The SPI port programs numerous parameters of the AD9874,
thus allowing the device to be optimized for any given application.
Programmable parameters include synthesizer divide ratios, AGC
attenuation and attack/decay time, received signal strength level,
decimation factor, output data format, 16 dB attenuator, and the
selected bias currents. The bias currents of the LNA and mixer
can be further reduced at the expense of degraded performance
for battery-powered applications.
FUNCTIONAL BLOCK DIAGRAM
MXOP MXON IF2P IF2N GCP GCN
–16dB
IFIN LNA
FREF
LO
SYN
DAC AGC
AD9874
-ADC
DECIMATION
FILTER
FORMATTING/SSI
CLK SYN
CONTROL LOGIC
VOLTAGE
REFERENCE
SPI
DOUTA
DOUTB
FS
CLKOUT
IOUTL
LOP LON
LO VCO AND
LOOP FILTER
IOUTC CLKP CLKN VREFP VCM VREFN PC PD PE SYNCB
LOOP FILTER
*Protected by U.S. Patent No. 5,969,657;
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






AD9874 Datasheet, Funktion
AD9874
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
MXOP 1
MXON 2
GNDF 3
IF2N 4
IF2P 5
VDDF 6
GCP 7
GCN 8
VDDA 9
GNDA 10
VREFP 11
VREFN 12
PIN 1
IDENTIFIER
AD9874
TOP VIEW
(Not to Scale)
36 GNDL
35 FREF
34 GNDS
33 SYNCB
32 GNDH
31 FS
30 DOUTB
29 DOUTA
28 CLKOUT
27 VDDH
26 VDDD
25 PE
13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description
1 MXOP
2 MXON
3 GNDF
4 IF2N
5 IF2P
6 VDDF
7 GCP
8 GCN
9 VDDA
10 GNDA
11 VREFP
12 VREFN
13 RREF
14 VDDQ
15 IOUTC
16 GNDQ
17 VDDC
18 GNDC
19 CLKP
20 CLKN
21 GNDS
22 GNDD
23 PC
24 PD
25 PE
26 VDDD
Mixer Output, Positive.
Mixer Output, Negative.
Ground for Front End of ADC.
Second IF Input (to ADC), Negative.
Second IF Input (to ADC), Positive.
Positive Power Supply for Front End of ADC.
Filter Capacitor for ADC Full-Scale Control.
Full-Scale Control Ground.
Positive Power Supply for ADC Back End.
Ground for ADC Back End.
Voltage Reference, Positive.
Voltage Reference, Negative.
Reference Resistor: Requires 100 kto
GNDA.
Positive Power Supply for Clock Synthesizer.
Clock Synthesizer Charge Pump Output
Current.
Ground for Clock Synthesizer Charge
Pump.
Positive Power Supply for Clock Synthesizer.
Ground for Clock Synthesizer.
Sampling Clock Input/Clock VCO Tank,
Positive.
Sampling Clock Input/Clock VCO Tank,
Negative.
Substrate Ground.
Ground for Digital Functions.
Clock Input for SPI Port.
Data I/O for SPI Port.
Enable Input for SPI Port.
Positive Power Supply for Internal Digital
Function.
Pin Mnemonic Description
27 VDDH
Positive Power Supply for Digital Interface.
28 CLKOUT Clock Output for SSI Port.
29 DOUTA Data Output for SSI Port.
30 DOUTB
Data Output for SSI Port (Inverted) or
SPI Port.
31 FS
Frame Sync for SSI Port.
32 GNDH
Ground for Digital Interface.
33 SYNCB
Resets SSI and Decimator Counters;
Active Low.
34 GNDS
Substrate Ground.
35 FREF
Reference Frequency Input for Both
Synthesizers.
36 GNDL
Ground for LO Synthesizer.
37 GNDP
Ground for LO Synthesizer Charge Pump.
38 IOUTL
LO Synthesizer Charge Pump Output
Current Charge Pump.
39 VDDP
Positive Power Supply for LO Synthesizer
Charge Pump.
40 VDDL
Positive Power Supply for LO Synthesizer.
41 CXVM
External Filter Capacitor; DC Output of
LNA.
42 LON
LO Input to Mixer and LO Synthesizer,
Negative.
43 LOP
LO Input to Mixer and LO Synthesizer,
Positive.
44 CXVL
External Bypass Capacitor for LNA Power
Supply.
45 GNDI
Ground for Mixer and LNA.
46 CXIF
External Capacitor for Mixer V-I Con-
verter Bias.
47 IFIN
First IF Input (to LNA).
48 VDDI
Positive Power Supply for LNA and Mixer.
–6– REV. A

6 Page









AD9874 pdf, datenblatt
AD9874
(VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = VDDx, VDDQ = VDDP = 5.0 V, fCLK = 18 MSPS, fIF = 109.56 MHz, fLO = 107.4 MHz,
TA = 25؇C, LO = –5 dBm, LO and CLK Synthesizer Disabled, 16-Bit Data with AGC and DVGA enabled, unless otherwise noted.)1
13
16-BIT w/DVGA
13
16-BIT w/DVGA
4
12 12
2
11 11
HIGH BIAS
0
10 10
24-BIT
–2
9 9 –4
24-BIT
8 8 –6
LOW BIAS
7 7 –8
6
0 50 100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
TPC 13a. Noise Figure vs. Frequency
(Minimum Attenuation, fCLK = 18 MSPS,
BW = 10 kHz, High Bias)
6
0 50 100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
TPC 13b. Noise Figure vs. Frequency
(Minimum Attenuation, fCLK = 18 MSPS,
BW = 10 kHz, Low Bias)
–10
0 50 100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
TPC 13c. Input IP3 vs. Frequency
(fCLK = 18 MSPS)
13
12
11
16-BIT w/DVGA
10
9
8
24-BIT
7
6
0 50 100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
TPC 14a. Noise Figure vs. Frequency
(Minimum Attenuation, fCLK = 26 MSPS,
BW = 24 kHz, High Bias)
13
16-BIT w/DVGA
12
11
10
9
8
24-BIT
7
6
0 50 100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
TPC 14b. Noise Figure vs. Frequency
(Minimum Attenuation, fCLK = 26 MSPS,
BW = 24 kHz, Low Bias)
2
HIGH BIAS
0
–2
–4
–6
LOW BIAS
–8
–10
0 50 100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
TPC 14c. Input IP3 vs. Frequency
(fCLK = 26 MSPS)
20.0
18.5
AGC
128
112
17.0 96
15.5 80
14.0 64
12.5
NOISE FIGURE
11.0
48
32
9.5 16
8.0 0
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INTERFERER LEVEL – dBm
TPC 15a. Noise Figure vs. Interferer
Level (16-Bit Data, BW = 12.5 kHz,
AGCR = 1, fINTERFERER = fIF + 110 kHz)
16
AGC ATTN
15
256
224
14 192
13 160
12 128
11 96
NOISE FIGURE
10 64
9 32
80
–50 –45 –40 –35 –30 –25 –20 –15 –10
INTERFERER LEVEL – dBm
TPC 15b. Noise Figure vs. Interferer
Level (16-Bit Data with DVGA, BW =
12.5 kHz, AGCR = 1, fINTERFERER =
fIF + 110 kHz)
16 128
15
AGC ATTN
14 96
13
12
NOISE FIGURE
11
64
10 32
9
8
–65 –55 –45 –35 –25 –15
INTERFERER LEVEL – dBm
0
–5
TPC 15c. Noise Figure vs. Interferer
Level (24-Bit Data, BW = 12.5 kHz,
AGCR = 1, fINTERFERER = fIF + 110 kHz)
1Data taken with Toko FSLM series 10 µH inductors.
2High Bias corresponds to LNA_Mixer Setting of 33 in SPI Register 0x01.
3Low Bias corresponds to LNA_Mixer Setting of 12 in SPI Register 0x01.
–12–
REV. A

12 Page





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