|
|
PDF HDH-12810CID Data sheet ( Hoja de datos )
| Número de pieza | HDH-12810CID | |
| Descripción | Couplers with Connectors (H Type) | |
| Fabricantes | Hirose Electric | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HDH-12810CID (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
|
No Preview Available !
Fibre Channel Transmitter and
Receiver Chipset
Technical Data
HDMP-1512 Transmitter
HDMP-1514 Receiver
Features
• ANSI X3.230-1994 Fibre
Channel Standard
Compatible (FC-0)
• Selectable 531.25 Mbaud or
1062.5 Mbaud Data Rates
• Selectable On Chip Laser
Driver and 50 Ω Cable
Driver
• TTL Compatible I/Os
• Single +5.0 V Power Supply
Applications
• Mass Storage System I/O
Channel
• Work Station/Server I/O
Channel
• High Speed Peripheral
Interface
Description
The HDMP-1512 transmitter and
the HDMP-1514 receiver are
bipolar integrated circuits,
separately packaged, in 80 pin M-
Quad packages. They are used to
build a high speed Fibre Channel
link for point to point data com-
munications. Shown in Figure 1 is
a typical full duplex point-to-
point Fibre Channel link. The
sending system provides parallel,
8B/10B, encoded data and a
transmit byte clock to the HDMP-
1512 transmitter. Using the trans-
mit byte clock, the transmitter
converts the data to a serial
stream and sends it over a copper
cable or fiber-optic link. The
receiver converts the serial data
stream back to parallel encoded
data and presents it, along with
the recovered transmit byte
clock, to the receiving system.
The sending system has the
option to electrically wrap the
transmitted data back to the local
receiver. It is possible to transmit
over the cable driver, or laser
driver when data is being
wrapped back to the local
receiver.
The two-chip set (transmitter
chip and receiver chip) is
compatible with the FC-0 layer of
the American National Standards
Institute (ANSI), Fibre Channel
specification, X3.230-1994. This
specification defines four
standard rates of operation for
Fibre Channel links. The HDMP-
1512 and HDMP-1514 chip-set
will operate at the two highest
defined serial rates of 531.25
Mbaud and 1062.5 Mbaud. These
serial baud rates correspond to
8B/10B encoded byte rates of 50
Mbytes/sec and 100 Mbytes/sec
respectively. The proper setting
of a single pin on each chip
selects the desired rate of
operation.
Several features, exclusive to this
chip-set, make it ideal for use in
Fibre Channel links. In addition,
the laser driver on the transmitter
chip, the dual loss of light
detectors on the receiver chip,
and the power supervisor and
power reset features make this
chip-set ideal for use with laser
optics. The serial cable driver
(transmitter chip), and the cable
equalizer (on the receiver chip),
can be operated in conjunction
with, or as an alternative to, the
laser driver. The laser driver can
also be driven directly with an
external high speed serial input.
Altogether, the various features,
input/output options, and
flexibility of this chip-set make
several unique link configurations
possible. In particular, it is ideally
suited for use in applications
where conformance to the FCSI
specification # 301-Rev 1.0,
Gbaud Link Module Specification,
is desired.
656 5964-6637E (4/96)
1 page  
capacitor on pin LZTC (# 27) will
begin to discharge. After
approximately 2 msec, the
voltage on LZTC falls to the fault
value and the error detector will
bring the FAULT pin (# 29) high
to alert the system. The error
detector will also hold the voltage
on LZMDF low, until a reset is
initiated.
The -LZON pin is used to disable
the laser driver under system
control or in conjunction with an
external open-fiber control (OFC)
chip. This pin is also used to
reset the error detector and
recharge the capacitor on pin
LZTC.
The LZPWRON pin, # 36, is used
to hold off dc power to the laser
driver until proper dc bias is
applied to the laser diode. When
LZPWRON goes high, the laser
driver is enabled, when it is low,
it is disabled. If not used, this pin
should be tied low.
Receiver Operation
The block diagram of the HDMP-
1514 receiver is shown in Figure
5. The functions included on the
receiver are a coaxial cable
equalizer, two independent loss
of light (LOL) detectors, an input
select function, monolithic phase
locked loop and clock recovery
circuits, a clock generator, frame
demultiplexer and comma
detector, power supply super-
visor, and output latch with TTL
drivers. Figures 20 and 21 show
schematically how to terminate
each pin on the HDMP-1514
when used in systems incorporat-
ing either copper or fiber media.
In the most basic sense, the
receiver accepts a serial electrical
data stream at 1062.5 Mbaud or
531.25 Mbaud and recovers the
8B/10B encoded parallel data and
clock that was applied to the
transmitter. Like the transmitter,
the receiver has several configu-
ration options which interrelate
according to the desired mode of
operation.
The two main modes of operation
for the receiver are based on the
desired signalling rate. The
signalling rate is controlled by
the proper setting of the SPDSEL
pin # 71. When this pin is set
low, the receiver operates at a
serial rate of 531.25 Mbaud.
When pin # 71 is set high, the
receiver operates at a serial rate
of 1062.5 Mbaud.
In a typical configuration, the
serial electrical data stream will
be applied to the ± DI pins, # 19
and # 20 on the receiver. The
serial electrical data stream may
have been transmitted over a
fiber optic link or a copper cable
link (several variations of each
link type is possible). For use
with copper links, a selectable
cable equalizer is available at the
input. This equalizer can be
switched into or out of the data
DR_REF
LOL
DETECTORS
± DI
-EQEN
± LIN
CABLE
EQUALIZER
INPUT
SELECT
VCC_HS
SUPPLY
SUPERVISOR
PLL AND
CLOCK
SELECT
INTERNAL
CLOCKS
CLOCK
GENERATOR
RBC0
RBC1
COM_DET
FRAME
DEMUX
AND
COMMA
DETECT
OUTPUT
10
LATCH AND
20
TTL
INTERFACE
10
DATA BYTE 0
Rx [00:09]
DATA BYTE 1
Rx [10:19]
Figure 5. HDMP-1514 (Receiver) Block Diagram.
660
5 Page 
HDMP-1512 (Tx)
Timing Characteristics
TC = 0°C to +85°C, VCC = 4.5 V to 5.5 V, PPSEL = 0, SPDSEL = 1
Symbol
Parameter
ts Setup Time
th
t_txlat
Hold Time
Transmit Lateny[1]
Units
nsec
nsec
nsec
Min.
Typ.
18
Max.
2
2.3
Note:
1. The Transmitter Latency is defined as the delay time from when a valid data word at TX[00:19] is clocked into the transmitter
(triggered by the rising edge of TBC during the time th) and when the first serial bit is transmitted on pins ± SO (defined by the
leading edge of the first bit transmitted).
HDMP-1514 (Rx)
Timing Characteristics
TC = 0°C to +85°C, VCC = 4.5 V to 5.5 V, PPSEL = 0, SPDSEL = 1
Symbol
Parameter
tflock
BLT
Frequency Lock Rate, Loop Filter Capacitor = 0.01 µF
Bit Lock Time
ts
th
ts’
th’
t_rxlat
Setup Time
Hold Time
Setup Time for Data Rx[10:19] in Ping-Pong Mode
Hold Time for Data Rx[10:19] in Ping-Pong Mode
Receive Latency[1]
Units
kHz/µsec
bit times
nsec
nsec
nsec
nsec
nsec
Min.
2.5
6.0
Typ.
100
6
8
38
Max.
2500
Note:
1. The Receiver Latency is defined as the delay time from receiving the first serial bit of a parallel data word (defined by the rising
edge of the first bit received at pins ± DI), and when that word is first clocked out at RX[00:19] (as defined by the falling edge of
RBC0 or RBC1, following time ts).
HDMP-1512 (Tx), HDMP-1514 (Rx)
Thermal Characteristics, TC = 0°C to +85°C
Symbol
Parameter
PD, Tx
Transmitter Power Dissipation, VCC = +5 V
PD, Rx
Θjc
Receiver Power Dissipation, VCC = +5 V
Thermal Resistance, Junction to Case
Units
Watt
Watt
°C/Watt
Typ.
1.6
2
12
I/O Type Definitions
I/O Type
Definition
I-TTL Input TTL. Floats high when left open.
O-TTL
O-BLL
I-H50
Output TTL.
50 Ω buffer line logic output driver. Should be ac coupled to drive 50 Ω loads. It can also
drive the I-H50 inputs through differential direct coupling. Note: all unused outputs should
be terminated with 50 Ω to VCC.
Input with internal 50 Ω terminations. Input is diode level shifted so that it can swing around
VCC. Can be driven with single-ended or differential, ac coupled configuration. To avoid
permanent damage, these inputs should not be connected to ground.
C External circuit node.
S Power supply or ground.
666
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet HDH-12810CID.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HDH-12810CID | Couplers with Connectors (H Type) | Hirose Electric |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |