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PCF8574 Schematic ( PDF Datasheet ) - Philips

Teilenummer PCF8574
Beschreibung Remote 8-bit I/O expander
Hersteller Philips
Logo Philips Logo 




Gesamt 24 Seiten
PCF8574 Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF8574
Remote 8-bit I/O expander for
I2C-bus
Product specification
Supersedes data of 2002 Jul 29
2002 Nov 22






PCF8574 Datasheet, Funktion
Philips Semiconductors
Remote 8-bit I/O expander for I2C-bus
5.2 SSOP20 package
SYMBOL
INT
SCL
n.c.
SDA
VDD
A0
A1
n.c.
A2
P0
P1
P2
n.c.
P3
VSS
P4
P5
n.c.
P6
P7
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
interrupt output (active LOW)
serial clock line
not connected
serial data line
supply voltage
address input 0
address input 1
not connected
address input 2
quasi-bidirectional I/O 0
quasi-bidirectional I/O 1
quasi-bidirectional I/O 2
not connected
quasi-bidirectional I/O 3
supply ground
quasi-bidirectional I/O 4
quasi-bidirectional I/O 5
not connected
quasi-bidirectional I/O 6
quasi-bidirectional I/O 7
DESCRIPTION
Product specification
PCF8574
handbook, halfpage
INT 1
20 P7
SCL 2
19 P6
n.c. 3
18 n.c.
SDA 4
17 P5
VDD 5 PCF8574TS 16 P4
A0 6 PCF8574ATS 15 VSS
A1 7
14 P3
n.c. 8
13 n.c.
A2 9
12 P2
P0 10
11 P1
MBD978
Fig.4 Pin configuration (SSOP20).
2002 Nov 22
6

6 Page









PCF8574 pdf, datenblatt
Philips Semiconductors
Remote 8-bit I/O expander for I2C-bus
Product specification
PCF8574
7.2 Interrupt output
The PCF8574 provides an open-drain output (INT) which
can be fed to a corresponding input of the microcontroller
(see Figs 13 and 14). This gives these chips a type of
master function which can initiate an action elsewhere in
the system.
An interrupt is generated by any rising or falling edge of the
port inputs in the input mode. After time tiv the signal INT is
valid.
Resetting and reactivating the interrupt circuit is achieved
when data on the port is changed to the original setting or
data is read from or written to the port which has generated
the interrupt.
Resetting occurs as follows:
In the READ mode at the acknowledge bit after the rising
edge of the SCL signal
In the WRITE mode at the acknowledge bit after the
HIGH-to-LOW transition of the SCL signal
Interrupts which occur during the acknowledge clock
pulse may be lost (or very short) due to the resetting of
the interrupt during this pulse.
Each change of the I/Os after resetting will be detected
and, after the next rising clock edge, will be transmitted as
INT. Reading from or writing to another device does not
affect the interrupt circuit.
7.3 Quasi-bidirectional I/Os
A quasi-bidirectional I/O can be used as an input or output
without the use of a control signal for data direction
(see Fig.15). At power-on the I/Os are HIGH. In this mode
only a current source to VDD is active. An additional strong
pull-up to VDD allows fast rising edges into heavily loaded
outputs. These devices turn on when an output is written
HIGH, and are switched off by the negative edge of SCL.
The I/Os should be HIGH before being used as inputs.
handbook, full pagewidth
MICROCONTROLLER
INT
V DD
PCF8574 PCF8574
(1) (2)
INT INT
PCF8574
(16)
INT
MBD976
Fig.13 Application of multiple PCF8574s with interrupt.
handbook, full pagewidth
slave address (PCF8574)
data from port
SDA S 0 1 0 0 A2 A1 A0 1 A
1
start condition
R/W acknowledge P5
from slave
SCL
1 234 567 8
DATA INTO
P5
INT
t iv
t ir
Fig.14 Interrupt generated by a change of input to I/O P5.
2002 Nov 22
12
1P
stop
condition
MBD972

12 Page





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