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PALCE22V10H-20 Schematic ( PDF Datasheet ) - AMD

Teilenummer PALCE22V10H-20
Beschreibung 24-Pin EE CMOS Versatile PAL Device
Hersteller AMD
Logo AMD Logo 




Gesamt 27 Seiten
PALCE22V10H-20 Datasheet, Funktion
FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-10/15/20/25
PALCE22V10 Family
24-Pin EE CMOS Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
s As fast as 5-ns propagation delay and
142.8 MHz fMAX (external)
s Low-power EE CMOS
s 10 macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
s Varied product term distribution allows up to
16 product terms per output for complex
functions
s Peripheral Component Interconnect (PCI)
compliant (-5/-7/-10)
GENERAL DESCRIPTION
The PALCE22V10 provides user-programmable logic
for replacing conventional SSI/MSI gates and flip-flops
at a reduced chip count.
The PAL device implements the familiar Boolean logic
transfer function, the sum of products. The PAL device
is a programmable AND array driving a fixed OR array.
The AND array is programmed to create custom product
terms, while the OR array sums selected terms at the
outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial, and active
BLOCK DIAGRAM
CLK/I0
1
s Global asynchronous reset and synchronous
preset for initialization
s Power-up reset for initialization and register
preload for testability
s Extensive third-party software and programmer
support through FusionPLD partners
s 24-pin SKINNYDIP, 24-pin SOIC, 24-pin Flat-
pack and 28-pin PLCC and LCC packages save
space
s 5-ns and 7.5-ns versions utilize split lead-
frames for improved performance
high or active low. The output configuration is
determined by two bits controlling two multiplexers in
each macrocell.
AMD’s FusionPLD program allows PALCE22V10 de-
signs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring that third-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
I1 - I11
11
8 10
Programmable
AND Array
(44 x 132)
12 14 16 16 14 12 10
8
RESET
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
OUTPUT
LOGIC
MACRO
CELL
PRESET
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5
Publication# 16564 Rev. D Amendment /0
Issue Date: February 1996
I/O6 I/O7 I/O8
I/O9 16564D-1
2-217






PALCE22V10H-20 Datasheet, Funktion
AMD
Programmable Three-State Outputs
Each output has a three-state output buffer with three-
state control. A product term controls the buffer, allow-
ing enable and disable to be a function of any product of
device inputs or output feedback. The combinatorial
output provides a bidirectional I/O pin, and may be con-
figured as a dedicated input if the buffer is always
disabled.
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Selection is controlled by programmable bit S0 in the
output macrocell, and affects both registered and com-
binatorial outputs. Selection is automatic, based on the
design specification and pin definitions. If the pin defini-
tion and output equation have the same polarity, the out-
put is programmed to be active high (S0 = 1).
Preset/Reset
For initialization, the PALCE22V10 has Preset and Re-
set product terms. These terms are connected to all reg-
istered outputs. When the Synchronous Preset (SP)
product term is asserted high, the output registers will be
loaded with a HIGH on the next LOW-to-HIGH clock
transition. When the Asynchronous Reset (AR) product
term is asserted high, the output registers will be imme-
diately loaded with a LOW independent of the clock.
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
Power-Up Reset
All flip-flops power-up to a logic LOW for predictable
system initialization. Outputs of the PALCE22V10 will
depend on the programmed output polarity. The VCC
rise must be monotonic and the reset delay time is
1000 ns maximum.
Register Preload
The register on the PALCE22V10 can be preloaded
from the output pins to facilitate functional testing of
complex state machine designs. This feature allows
direct loading of arbitrary states, making it unnecessary
to cycle through long test vector sequences to reach a
desired state. In addition, transitions from illegal states
can be verified by loading illegal states and observing
proper recovery.
Security Bit
After programming and verification, a PALCE22V10 de-
sign can be secured by programming the security EE bit.
Once programmed, this bit defeats readback of the in-
ternal programmed pattern by a device programmer, se-
curing proprietary designs from competitors. When the
security bit is programmed, the array will read as if every
bit is erased, and preload will be disabled.
The bit can only be erased in conjunction with erasure of
the entire pattern.
Programming and Erasing
The PALCE22V10 can be programmed on standard
logic programmers. It also may be erased to reset a pre-
viously configured device back to its virgin state. Era-
sure is automatically performed by the programming
hardware. No special erase operation is required.
Quality and Testability
The PALCE22V10 offers a very high level of built-in
quality. The erasability of the device provides a direct
means of verifying performance of all AC and DC pa-
rameters. In addition, this verifies complete program-
mability and functionality of the device to provide the
highest programming yields and post-programming
functional yields in the industry.
Technology
The high-speed PALCE22V10 is fabricated with AMD’s
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clear switching.
PCI Compliance
The PALCE22V10H-5/7/10 is fully compliant with the
PCI Local Bus Specification published by the PCI Spe-
cial Interest Group. The PALCE22V10H-5/7/10’s pre-
dictable timing ensures compliance with the PCI AC
specifications independent of the design.
2-222
PALCE22V10 Family

6 Page









PALCE22V10H-20 pdf, datenblatt
AMD
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . –65°C to +150°C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . –55°C to +125°C
Supply Voltage with Respect
to Ground . . . . . . . . . . . . . . . . . . . . –0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 1.0 V
DC Output or I/O Pin
Voltage . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 1.0 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = 0°C to +75°C) . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maxi-
mum ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC) with
Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
Operating Ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min Max Unit
VOH Output HIGH Voltage
IOH = –3.2 mA
VIN = VIH or VIL
VCC = Min
2.4
V
VOL Output LOW Voltage
IOL = 16 mA
VIN = VIH or VIL
VCC = Min
0.4 V
VIH Input HIGH Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
V
VIL Input LOW Voltage
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8 V
IIH Input HIGH Leakage Current VIN = VCC, VCC = Max (Note 2)
10 µA
IIL
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 2)
–100
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = VCC, VCC = Max,
VIN = VIL or VIH (Note 2)
10 µA
IOZL Off-State Output Leakage VOUT = 0 V, VCC = Max
Current LOW
VIN = VIL or VIH (Note 2)
–100
µA
ISC Output Short-Circuit
Current
VOUT = 0.5 V, VCC = Max
TA = 25° C (Note 3)
–30 –130 mA
ICC
(Dynamic)
Supply Current
Outputs Open, (IOUT = 0 mA),
VCC = Max, f = 25 MHz
120 mA
Notes:
1. These are absolute values with respect to the device ground and all overshoots due to system and tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
2-228
PALCE22V10H-10 (Com’l)

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